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159 lines
6.2 KiB
LLVM
159 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=GCN,SI
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; RUN: llc < %s -march=amdgcn -mcpu=fiji -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=GCN,VI
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; Make sure high constant 0 isn't pointlessly materialized
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define i16 @trunc_bitcast_i64_lshr_32_i16(i64 %bar) {
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; GCN-LABEL: trunc_bitcast_i64_lshr_32_i16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%srl = lshr i64 %bar, 32
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%trunc = trunc i64 %srl to i16
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ret i16 %trunc
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}
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define i32 @trunc_bitcast_i64_lshr_32_i32(i64 %bar) {
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; GCN-LABEL: trunc_bitcast_i64_lshr_32_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%srl = lshr i64 %bar, 32
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%trunc = trunc i64 %srl to i32
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ret i32 %trunc
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}
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define i16 @trunc_bitcast_v2i32_to_i16(<2 x i32> %bar) {
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; SI-LABEL: trunc_bitcast_v2i32_to_i16:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_add_i32_e32 v0, vcc, 4, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: trunc_bitcast_v2i32_to_i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: flat_load_dword v0, v[0:1]
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; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VI-NEXT: v_add_u16_e32 v0, 4, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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%load0 = load i32, i32 addrspace(1)* undef
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%load1 = load i32, i32 addrspace(1)* null
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%insert.0 = insertelement <2 x i32> undef, i32 %load0, i32 0
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%insert.1 = insertelement <2 x i32> %insert.0, i32 99, i32 1
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%bc = bitcast <2 x i32> %insert.1 to i64
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%trunc = trunc i64 %bc to i16
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%add = add i16 %trunc, 4
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ret i16 %add
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}
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; Make sure there's no crash if the source vector type is FP
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define i16 @trunc_bitcast_v2f32_to_i16(<2 x float> %bar) {
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; SI-LABEL: trunc_bitcast_v2f32_to_i16:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_add_i32_e32 v0, vcc, 4, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: trunc_bitcast_v2f32_to_i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: flat_load_dword v0, v[0:1]
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; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VI-NEXT: v_add_u16_e32 v0, 4, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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%load0 = load float, float addrspace(1)* undef
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%load1 = load float, float addrspace(1)* null
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%insert.0 = insertelement <2 x float> undef, float %load0, i32 0
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%insert.1 = insertelement <2 x float> %insert.0, float 4.0, i32 1
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%bc = bitcast <2 x float> %insert.1 to i64
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%trunc = trunc i64 %bc to i16
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%add = add i16 %trunc, 4
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ret i16 %add
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}
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define amdgpu_kernel void @truncate_high_elt_extract_vector(<2 x i16> addrspace(1)* nocapture readonly %arg, <2 x i16> addrspace(1)* nocapture readonly %arg1, <2 x i16> addrspace(1)* nocapture %arg2) local_unnamed_addr {
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; SI-LABEL: truncate_high_elt_extract_vector:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_load_dword s4, s[4:5], 0x0
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; SI-NEXT: s_load_dword s5, s[6:7], 0x0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_sext_i32_i16 s4, s4
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; SI-NEXT: s_sext_i32_i16 s5, s5
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: v_mul_i32_i24_e32 v0, s5, v0
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; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: truncate_high_elt_extract_vector:
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; VI: ; %bb.0: ; %bb
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_load_dword s2, s[4:5], 0x0
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; VI-NEXT: s_load_dword s3, s[6:7], 0x0
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; VI-NEXT: v_mov_b32_e32 v0, s0
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_sext_i32_i16 s0, s2
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; VI-NEXT: s_sext_i32_i16 s1, s3
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; VI-NEXT: v_mov_b32_e32 v2, s0
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; VI-NEXT: v_mul_i32_i24_e32 v2, s1, v2
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; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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bb:
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%tmp = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg, i64 undef
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%tmp3 = load <2 x i16>, <2 x i16> addrspace(1)* %tmp, align 4
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%tmp4 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg1, i64 undef
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%tmp5 = load <2 x i16>, <2 x i16> addrspace(1)* %tmp4, align 4
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%tmp6 = sext <2 x i16> %tmp3 to <2 x i32>
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%tmp7 = sext <2 x i16> %tmp5 to <2 x i32>
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%tmp8 = extractelement <2 x i32> %tmp6, i64 0
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%tmp9 = extractelement <2 x i32> %tmp7, i64 0
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%tmp10 = mul nsw i32 %tmp9, %tmp8
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%tmp11 = insertelement <2 x i32> undef, i32 %tmp10, i32 0
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%tmp12 = insertelement <2 x i32> %tmp11, i32 undef, i32 1
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%tmp13 = lshr <2 x i32> %tmp12, <i32 16, i32 16>
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%tmp14 = trunc <2 x i32> %tmp13 to <2 x i16>
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%tmp15 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg2, i64 undef
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store <2 x i16> %tmp14, <2 x i16> addrspace(1)* %tmp15, align 4
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ret void
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}
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define <2 x i16> @trunc_v2i64_arg_to_v2i16(<2 x i64> %arg0) #0 {
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; SI-LABEL: trunc_v2i64_arg_to_v2i16:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
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; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; SI-NEXT: v_or_b32_e32 v0, v0, v1
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; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: trunc_v2i64_arg_to_v2i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
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; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: s_setpc_b64 s[30:31]
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%trunc = trunc <2 x i64> %arg0 to <2 x i16>
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ret <2 x i16> %trunc
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}
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