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68d9df2738
Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. But the special condition is that the element number is 1, such as <1 x i128>. So just early exit to fix the assert. Patch By: wuzish (Zixuan Wu) Differential Revision: https://reviews.llvm.org/D52072 llvm-svn: 342611
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
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define void @test1(i1 %x, i8 %x2, i8* %x3, i64 %x4) {
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entry:
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%tmp3 = and i64 %x4, 16
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%bf.shl = trunc i64 %tmp3 to i8
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%bf.clear = and i8 %x2, -17
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%bf.set = or i8 %bf.shl, %bf.clear
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br i1 %x, label %if.then, label %if.end
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if.then:
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ret void
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if.end:
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store i8 %bf.set, i8* %x3, align 4
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ret void
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}
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; A BUILD_VECTOR of 1 element caused a crash in combineBVOfConsecutiveLoads()
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; Test that this is no longer the case
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define signext i32 @test2() {
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entry:
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%retval = alloca i32, align 4
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%__a = alloca i128, align 16
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%b = alloca i64, align 8
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store i32 0, i32* %retval, align 4
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%0 = load i128, i128* %__a, align 16
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %0, i32 0
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%splat.splat = shufflevector <1 x i128> %splat.splatinsert, <1 x i128> undef, <1 x i32> zeroinitializer
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%1 = bitcast <1 x i128> %splat.splat to <2 x i64>
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%2 = extractelement <2 x i64> %1, i32 0
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store i64 %2, i64* %b, align 8
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ret i32 0
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}
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