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8a8b34bbc9
Duplicating this intrinsic is not generally valid because it has the side-effect of decrementing the CTR. Any passes that duplicate it would need to be taught to keep the regions formed completely disjoint. This patch should be NFC for typical uses as CTRLoops runs after the remaining loop passes. It only affects situations where the loop passes are scheduled on the IR after the codegen passes (as is the case with some JIT pipelines). Fixes https://bugs.llvm.org/show_bug.cgi?id=37050 llvm-svn: 330186
76 lines
2.4 KiB
LLVM
76 lines
2.4 KiB
LLVM
; RUN: opt -early-cse-memssa -loop-rotate -licm -loop-rotate -S %s -o - | FileCheck %s
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; ModuleID = 'bugpoint-reduced-simplified.bc'
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source_filename = "bugpoint-output-8903f29.bc"
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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define void @test(i64 %arg.ssa, i64 %arg.nb) local_unnamed_addr {
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; Ensure that loop rotation doesn't duplicate the call to
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; llvm.ppc.is.decremented.ctr.nonzero
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; CHECK-LABEL: test
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; CHECK: call i1 @llvm.ppc.is.decremented.ctr.nonzero
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; CHECK-NOT: call i1 @llvm.ppc.is.decremented.ctr.nonzero
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; CHECK: declare i1 @llvm.ppc.is.decremented.ctr.nonzero
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entry:
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switch i32 undef, label %BB_8 [
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i32 -2, label %BB_9
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i32 0, label %BB_9
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]
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BB_1: ; preds = %BB_12, %BB_4
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%bcount.1.us = phi i64 [ %.810.us, %BB_4 ], [ 0, %BB_12 ]
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%0 = add i64 %arg.ssa, %bcount.1.us
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%.568.us = load i32, i32* undef, align 4
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%.15.i.us = icmp slt i32 0, %.568.us
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br i1 %.15.i.us, label %BB_3, label %BB_2
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BB_2: ; preds = %BB_1
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%.982.us = add nsw i64 %0, 1
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unreachable
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BB_3: ; preds = %BB_1
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%1 = add i64 %arg.ssa, %bcount.1.us
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%2 = add i64 %1, 1
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%3 = call i1 @llvm.ppc.is.decremented.ctr.nonzero()
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br i1 %3, label %BB_4, label %BB_7
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BB_4: ; preds = %BB_3
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%.810.us = add nuw nsw i64 %bcount.1.us, 1
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br label %BB_1
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BB_5: ; preds = %BB_7, %BB_5
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%lsr.iv20.i116 = phi i64 [ %2, %BB_7 ], [ %lsr.iv.next21.i126, %BB_5 ]
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%lsr.iv.next21.i126 = add i64 %lsr.iv20.i116, 1
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br i1 undef, label %BB_5, label %BB_6
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BB_6: ; preds = %BB_5
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ret void
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BB_7: ; preds = %BB_3
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br label %BB_5
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BB_8: ; preds = %entry
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ret void
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BB_9: ; preds = %entry, %entry
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br label %BB_10
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BB_10: ; preds = %BB_9
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br label %BB_11
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BB_11: ; preds = %BB_11, %BB_10
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br i1 undef, label %BB_11, label %BB_12
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BB_12: ; preds = %BB_11
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call void @llvm.ppc.mtctr.i64(i64 %arg.nb)
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br label %BB_1
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}
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; Function Attrs: nounwind
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declare void @llvm.ppc.mtctr.i64(i64) #0
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; Function Attrs: nounwind
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declare i1 @llvm.ppc.is.decremented.ctr.nonzero() #0
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attributes #0 = { nounwind }
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