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25fcb83d99
All tests with -run-pass !=none should not in MIR/, See MIR/README. ``` Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As a rule of thumb this directory should only contain tests using 'llc -run-pass none'. ``` llvm-svn: 371857
68 lines
2.3 KiB
YAML
68 lines
2.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -run-pass=ppc-mi-peepholes \
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# RUN: -simplify-mir %s -o - | FileCheck %s
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---
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name: poc
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alignment: 16
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: poc
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1, %bb.2
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; CHECK: liveins: $x3, $x4, $x5, $x6
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; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x6
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; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x5
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; CHECK: [[COPY2:%[0-9]+]]:g8rc = COPY $x4
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; CHECK: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
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; CHECK: [[ANDIo8_:%[0-9]+]]:g8rc = ANDIo8 [[COPY1]], 1, implicit-def $cr0
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; CHECK: [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
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; CHECK: BCn killed [[COPY4]], %bb.2
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; CHECK: B %bb.1
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; CHECK: bb.1:
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; CHECK: liveins: $x3
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; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
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; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
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; CHECK: $x3 = COPY [[RLDICR]]
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; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
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; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
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; CHECK: $x3 = COPY [[ADD8_]]
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; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
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; CHECK: bb.2:
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; CHECK: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
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; CHECK: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
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; CHECK: $x3 = COPY [[INSERT_SUBREG]]
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; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: $x3, $x4, $x5, $x6
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%4:g8rc = COPY $x6
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%3:g8rc = COPY $x5
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%2:g8rc = COPY $x4
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%1:g8rc_and_g8rc_nox0 = COPY $x3
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%11:g8rc = ANDIo8 %3, 1, implicit-def $cr0
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%6:crbitrc = COPY $cr0gt
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BCn killed %6, %bb.2
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B %bb.1
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bb.1:
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liveins: $x3
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%0:g8rc = EXTSW $x3
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%12:g8rc = RLDICR %11, 2, 61
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$x3 = COPY %12:g8rc
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%9:g8rc = RLDICR %0, 2, 61
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%10:g8rc = ADD8 %1, %9
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$x3 = COPY %10
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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bb.2:
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%5:gprc = COPY %4.sub_32
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%8:g8rc = IMPLICIT_DEF
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%7:g8rc = INSERT_SUBREG %8, %5, %subreg.sub_32
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$x3 = COPY %7
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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