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699d18eb82
Fix assert about using an undefined physical register in machine instruction verify pass. The reason is that register flag undef is missing when doing transformation from If Conversion Pass. ``` Bad machine code: Using an undefined physical register - function: func_65 - basic block: %bb.0 entry (0x10024740738) - instruction: BCLR killed $cr5lt, implicit $lr8, implicit $rm, implicit undef $x3 - operand 0: killed $cr5lt LLVM ERROR: Found 1 machine code errors. ``` There are also other existing testcases with same issue. So I add -verify-machineinstrs option to open verifying. Differential Revision: https://reviews.llvm.org/D55408 llvm-svn: 348566
49 lines
1.8 KiB
LLVM
49 lines
1.8 KiB
LLVM
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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@multvec_i = external unnamed_addr global [100 x i32], align 4
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define fastcc void @subs_STMultiExceptIntern(i32 %input) nounwind {
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entry:
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br i1 undef, label %while.body.lr.ph, label %return
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while.body.lr.ph: ; preds = %entry
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br label %while.body
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while.body: ; preds = %if.end12, %while.body.lr.ph
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%i.0240 = phi i32 [ -1, %while.body.lr.ph ], [ %i.1, %if.end12 ]
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br i1 undef, label %if.end12, label %if.then
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if.then: ; preds = %while.body
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%0 = add i32 %input, 1
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br label %if.end12
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if.end12: ; preds = %if.then, %while.body
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%i.1 = phi i32 [ %i.0240, %while.body ], [ %0, %if.then ]
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br i1 undef, label %while.body, label %while.end
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while.end: ; preds = %if.end12
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br i1 undef, label %return, label %if.end15
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if.end15: ; preds = %while.end
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%idxprom.i.i230 = sext i32 %i.1 to i64
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%arrayidx18 = getelementptr inbounds [100 x i32], [100 x i32]* @multvec_i, i64 0, i64 %idxprom.i.i230
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store i32 0, i32* %arrayidx18, align 4
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br i1 undef, label %while.body21, label %while.end90
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while.body21: ; preds = %if.end15
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unreachable
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while.end90: ; preds = %if.end15
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store i32 0, i32* %arrayidx18, align 4
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br label %return
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return: ; preds = %while.end90, %while.end, %entry
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ret void
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; CHECK: @subs_STMultiExceptIntern
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; CHECK: stwux
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}
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