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b2118cf9ea
Add a new file to test the code gen for common linkage symbol. Remove common linkage in some other testcases to avoid distraction. llvm-svn: 372426
238 lines
7.3 KiB
LLVM
238 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = local_unnamed_addr global i64 0, align 8
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define i64 @test_llneull(i64 %a, i64 %b) {
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; CHECK-LABEL: test_llneull:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addic r4, r3, -1
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; CHECK-NEXT: subfe r3, r4, r3
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_llneull:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xor r3, r3, r4
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; CHECK-BE-NEXT: addic r4, r3, -1
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; CHECK-BE-NEXT: subfe r3, r4, r3
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_llneull:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: addic r4, r3, -1
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; CHECK-LE-NEXT: subfe r3, r4, r3
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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}
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define i64 @test_llneull_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_llneull_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: subfic r3, r3, 0
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; CHECK-NEXT: subfe r3, r3, r3
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_llneull_sext:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xor r3, r3, r4
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; CHECK-BE-NEXT: subfic r3, r3, 0
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; CHECK-BE-NEXT: subfe r3, r3, r3
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_llneull_sext:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: subfic r3, r3, 0
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; CHECK-LE-NEXT: subfe r3, r3, r3
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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}
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define i64 @test_llneull_z(i64 %a) {
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; CHECK-LABEL: test_llneull_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addic r4, r3, -1
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; CHECK-NEXT: subfe r3, r4, r3
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_llneull_z:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addic r4, r3, -1
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; CHECK-BE-NEXT: subfe r3, r4, r3
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_llneull_z:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addic r4, r3, -1
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; CHECK-LE-NEXT: subfe r3, r4, r3
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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}
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define i64 @test_llneull_sext_z(i64 %a) {
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; CHECK-LABEL: test_llneull_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: subfic r3, r3, 0
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; CHECK-NEXT: subfe r3, r3, r3
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_llneull_sext_z:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: subfic r3, r3, 0
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; CHECK-BE-NEXT: subfe r3, r3, r3
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_llneull_sext_z:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: subfic r3, r3, 0
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; CHECK-LE-NEXT: subfe r3, r3, r3
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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}
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define void @test_llneull_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_llneull_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addis r5, r2, glob@toc@ha
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; CHECK-NEXT: addic r4, r3, -1
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; CHECK-NEXT: subfe r3, r4, r3
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; CHECK-NEXT: std r3, glob@toc@l(r5)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_llneull_store:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-BE-NEXT: xor r3, r3, r4
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; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-BE-NEXT: addic r5, r3, -1
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; CHECK-BE-NEXT: subfe r3, r5, r3
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; CHECK-BE-NEXT: std r3, 0(r4)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_llneull_store:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
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; CHECK-LE-NEXT: addic r4, r3, -1
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; CHECK-LE-NEXT: subfe r3, r4, r3
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; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_llneull_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_llneull_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addis r5, r2, glob@toc@ha
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; CHECK-NEXT: subfic r3, r3, 0
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; CHECK-NEXT: subfe r3, r3, r3
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; CHECK-NEXT: std r3, glob@toc@l(r5)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_llneull_sext_store:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-BE-NEXT: xor r3, r3, r4
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; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-BE-NEXT: subfic r3, r3, 0
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; CHECK-BE-NEXT: subfe r3, r3, r3
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; CHECK-BE-NEXT: std r3, 0(r4)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_llneull_sext_store:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
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; CHECK-LE-NEXT: subfic r3, r3, 0
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; CHECK-LE-NEXT: subfe r3, r3, r3
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; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_llneull_z_store(i64 %a) {
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; CHECK-LABEL: test_llneull_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addic r5, r3, -1
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; CHECK-NEXT: addis r4, r2, glob@toc@ha
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; CHECK-NEXT: subfe r3, r5, r3
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; CHECK-NEXT: std r3, glob@toc@l(r4)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_llneull_z_store:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-BE-NEXT: addic r5, r3, -1
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; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-BE-NEXT: subfe r3, r5, r3
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; CHECK-BE-NEXT: std r3, 0(r4)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_llneull_z_store:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addic r5, r3, -1
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; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
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; CHECK-LE-NEXT: subfe r3, r5, r3
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; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_llneull_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_llneull_sext_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: subfic r3, r3, 0
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; CHECK-NEXT: addis r4, r2, glob@toc@ha
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; CHECK-NEXT: subfe r3, r3, r3
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; CHECK-NEXT: std r3, glob@toc@l(r4)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_llneull_sext_z_store:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-BE-NEXT: subfic r3, r3, 0
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; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-BE-NEXT: subfe r3, r3, r3
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; CHECK-BE-NEXT: std r3, 0(r4)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_llneull_sext_z_store:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: subfic r3, r3, 0
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; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
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; CHECK-LE-NEXT: subfe r3, r3, r3
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; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp ne i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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