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https://github.com/RPCS3/llvm-mirror.git
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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
518 lines
11 KiB
LLVM
518 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; These tests are each targeted at a particular RISC-V ALU instruction. Other
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; files in this folder exercise LLVM IR instructions that don't directly match a
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; RISC-V instruction. This file contains tests for the instructions common
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; between RV32I and RV64I as well as the *W instructions introduced in RV64I.
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; Register-immediate instructions
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define i64 @addi(i64 %a) nounwind {
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; RV64I-LABEL: addi:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: addi:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a2, a0, 1
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: add a1, a1, a0
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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%1 = add i64 %a, 1
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ret i64 %1
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}
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define i64 @slti(i64 %a) nounwind {
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; RV64I-LABEL: slti:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slti a0, a0, 2
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: slti:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a1, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: slti a0, a1, 0
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: sltiu a0, a0, 2
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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%1 = icmp slt i64 %a, 2
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%2 = zext i1 %1 to i64
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ret i64 %2
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}
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define i64 @sltiu(i64 %a) nounwind {
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; RV64I-LABEL: sltiu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltiu a0, a0, 3
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: sltiu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a1, .LBB2_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: sltiu a0, a0, 3
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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%1 = icmp ult i64 %a, 3
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%2 = zext i1 %1 to i64
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ret i64 %2
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}
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define i64 @xori(i64 %a) nounwind {
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; RV64I-LABEL: xori:
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; RV64I: # %bb.0:
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; RV64I-NEXT: xori a0, a0, 4
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: xori:
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; RV32I: # %bb.0:
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; RV32I-NEXT: xori a0, a0, 4
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; RV32I-NEXT: ret
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%1 = xor i64 %a, 4
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ret i64 %1
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}
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define i64 @ori(i64 %a) nounwind {
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; RV64I-LABEL: ori:
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; RV64I: # %bb.0:
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; RV64I-NEXT: ori a0, a0, 5
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: ori:
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; RV32I: # %bb.0:
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; RV32I-NEXT: ori a0, a0, 5
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; RV32I-NEXT: ret
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%1 = or i64 %a, 5
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ret i64 %1
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}
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define i64 @andi(i64 %a) nounwind {
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; RV64I-LABEL: andi:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 6
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: andi:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 6
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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%1 = and i64 %a, 6
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ret i64 %1
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}
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define i64 @slli(i64 %a) nounwind {
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; RV64I-LABEL: slli:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 7
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: slli:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a2, a0, 25
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; RV32I-NEXT: slli a1, a1, 7
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: slli a0, a0, 7
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; RV32I-NEXT: ret
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%1 = shl i64 %a, 7
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ret i64 %1
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}
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define i64 @srli(i64 %a) nounwind {
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; RV64I-LABEL: srli:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 8
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: srli:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a1, 24
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; RV32I-NEXT: srli a0, a0, 8
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: srli a1, a1, 8
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; RV32I-NEXT: ret
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%1 = lshr i64 %a, 8
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ret i64 %1
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}
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define i64 @srai(i64 %a) nounwind {
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; RV64I-LABEL: srai:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srai a0, a0, 9
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: srai:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a1, 23
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; RV32I-NEXT: srli a0, a0, 9
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: srai a1, a1, 9
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; RV32I-NEXT: ret
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%1 = ashr i64 %a, 9
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ret i64 %1
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}
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; Register-register instructions
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define i64 @add(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: add:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: add:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a1, a1, a3
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; RV32I-NEXT: add a2, a0, a2
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: add a1, a1, a0
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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%1 = add i64 %a, %b
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ret i64 %1
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}
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define i64 @sub(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: sub:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sub a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: sub:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a4, a0, a2
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sub a1, a1, a4
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: ret
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%1 = sub i64 %a, %b
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ret i64 %1
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}
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define i64 @sll(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: sll:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sll a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: sll:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB11_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sll a1, a0, a3
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB11_2:
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; RV32I-NEXT: sll a1, a1, a2
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: srli a4, a0, 1
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; RV32I-NEXT: srl a3, a4, a3
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: sll a2, a0, a2
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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%1 = shl i64 %a, %b
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ret i64 %1
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}
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define i64 @slt(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: slt:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slt a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: slt:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB12_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: slt a0, a1, a3
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB12_2:
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; RV32I-NEXT: sltu a0, a0, a2
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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%1 = icmp slt i64 %a, %b
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%2 = zext i1 %1 to i64
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ret i64 %2
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}
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define i64 @sltu(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: sltu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: sltu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB13_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a0, a1, a3
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB13_2:
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; RV32I-NEXT: sltu a0, a0, a2
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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%1 = icmp ult i64 %a, %b
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%2 = zext i1 %1 to i64
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ret i64 %2
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}
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define i64 @xor(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: xor:
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; RV64I: # %bb.0:
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: xor:
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; RV32I: # %bb.0:
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: xor a1, a1, a3
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; RV32I-NEXT: ret
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%1 = xor i64 %a, %b
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ret i64 %1
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}
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define i64 @srl(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: srl:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srl a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: srl:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB15_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srl a0, a1, a3
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB15_2:
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: slli a4, a1, 1
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; RV32I-NEXT: sll a3, a4, a3
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: srl a2, a1, a2
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; RV32I-NEXT: mv a1, a2
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; RV32I-NEXT: ret
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%1 = lshr i64 %a, %b
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ret i64 %1
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}
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define i64 @sra(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: sra:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sra a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: sra:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB16_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sra a0, a1, a3
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; RV32I-NEXT: srai a1, a1, 31
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB16_2:
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: slli a4, a1, 1
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; RV32I-NEXT: sll a3, a4, a3
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: sra a1, a1, a2
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; RV32I-NEXT: ret
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%1 = ashr i64 %a, %b
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ret i64 %1
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}
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define i64 @or(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: or:
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; RV64I: # %bb.0:
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: or:
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; RV32I: # %bb.0:
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: ret
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%1 = or i64 %a, %b
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ret i64 %1
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}
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define i64 @and(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: and:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: and:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: and a1, a1, a3
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; RV32I-NEXT: ret
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%1 = and i64 %a, %b
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ret i64 %1
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}
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; RV64I-only instructions
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define signext i32 @addiw(i32 signext %a) nounwind {
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; RV64I-LABEL: addiw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addiw a0, a0, 123
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: addiw:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 123
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; RV32I-NEXT: ret
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%1 = add i32 %a, 123
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ret i32 %1
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}
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define signext i32 @slliw(i32 signext %a) nounwind {
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; RV64I-LABEL: slliw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slliw a0, a0, 17
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: slliw:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 17
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; RV32I-NEXT: ret
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%1 = shl i32 %a, 17
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ret i32 %1
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}
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define signext i32 @srliw(i32 %a) nounwind {
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; RV64I-LABEL: srliw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srliw a0, a0, 8
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: srliw:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 8
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; RV32I-NEXT: ret
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%1 = lshr i32 %a, 8
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ret i32 %1
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}
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define signext i32 @sraiw(i32 %a) nounwind {
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; RV64I-LABEL: sraiw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraiw a0, a0, 9
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: sraiw:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a0, a0, 9
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; RV32I-NEXT: ret
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%1 = ashr i32 %a, 9
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ret i32 %1
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}
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define signext i32 @sextw(i32 zeroext %a) nounwind {
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; RV64I-LABEL: sextw:
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|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sext.w a0, a0
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: sextw:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: ret
|
|
ret i32 %a
|
|
}
|
|
|
|
define signext i32 @addw(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: addw:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: addw:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: add a0, a0, a1
|
|
; RV32I-NEXT: ret
|
|
%1 = add i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @subw(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: subw:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: subw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: subw:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: sub a0, a0, a1
|
|
; RV32I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sllw(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sllw:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: sllw:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: sll a0, a0, a1
|
|
; RV32I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @srlw(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: srlw:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: srlw:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: srl a0, a0, a1
|
|
; RV32I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sraw(i64 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sraw:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV32I-LABEL: sraw:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: sra a0, a0, a2
|
|
; RV32I-NEXT: ret
|
|
%1 = trunc i64 %a to i32
|
|
%2 = ashr i32 %1, %b
|
|
ret i32 %2
|
|
}
|