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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
62 lines
2.0 KiB
LLVM
62 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IFD %s
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define double @double_imm() nounwind {
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; TODO: Should probably prefer fld or ld on RV64 rather than materialising an
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; expensive constant.
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;
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; RV32IFD-LABEL: double_imm:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: lui a0, 345155
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; RV32IFD-NEXT: addi a0, a0, -744
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; RV32IFD-NEXT: lui a1, 262290
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; RV32IFD-NEXT: addi a1, a1, 507
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: double_imm:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: lui a0, 512
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; RV64IFD-NEXT: addiw a0, a0, 1169
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; RV64IFD-NEXT: slli a0, a0, 15
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; RV64IFD-NEXT: addi a0, a0, -299
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; RV64IFD-NEXT: slli a0, a0, 14
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; RV64IFD-NEXT: addi a0, a0, 1091
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; RV64IFD-NEXT: slli a0, a0, 12
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; RV64IFD-NEXT: addi a0, a0, -744
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; RV64IFD-NEXT: ret
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ret double 3.1415926535897931159979634685441851615905761718750
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}
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define double @double_imm_op(double %a) nounwind {
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; RV32IFD-LABEL: double_imm_op:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
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; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
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; RV32IFD-NEXT: fld ft1, 0(a0)
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; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: double_imm_op:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: lui a1, %hi(.LCPI1_0)
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; RV64IFD-NEXT: addi a1, a1, %lo(.LCPI1_0)
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; RV64IFD-NEXT: fld ft0, 0(a1)
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = fadd double %a, 1.0
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ret double %1
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}
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