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c702b7f668
-mcpu=# will support:
. generic: the default insn set
. v1: insn set version 1, the same as generic
. v2: insn set version 2, version 1 + additional jmp insns
. probe: the compiler will probe the underlying kernel to
decide proper version of insn set.
We did not not use -mcpu=native since llc/llvm will interpret -mcpu=native
as the underlying hardware architecture regardless of -march value.
Currently, only x86_64 supports -mcpu=probe. Other architecture will
silently revert to "generic".
Also added -mcpu=help to print available cpu parameters.
llvm will print out the information only if there are at least one
cpu and at least one feature. Add an unused dummy feature to
enable the printout.
Examples for usage:
$ llc -march=bpf -mcpu=v1 -filetype=asm t.ll
$ llc -march=bpf -mcpu=v2 -filetype=asm t.ll
$ llc -march=bpf -mcpu=generic -filetype=asm t.ll
$ llc -march=bpf -mcpu=probe -filetype=asm t.ll
$ llc -march=bpf -mcpu=v3 -filetype=asm t.ll
'v3' is not a recognized processor for this target (ignoring processor)
...
$ llc -march=bpf -mcpu=help -filetype=asm t.ll
Available CPUs for this target:
generic - Select the generic processor.
probe - Select the probe processor.
v1 - Select the v1 processor.
v2 - Select the v2 processor.
Available features for this target:
dummy - unused feature.
Use +feature to enable a feature, or -feature to disable it.
For example, llc -mcpu=mycpu -mattr=+feature1,-feature2
...
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 311522
113 lines
2.4 KiB
LLVM
113 lines
2.4 KiB
LLVM
; RUN: llc -march=bpfel < %s | FileCheck --check-prefix=CHECK-V1 %s
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; RUN: llc -march=bpfel -mcpu=v2 < %s | FileCheck --check-prefix=CHECK-V2 %s
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define i16 @sccweqand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp eq i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK-LABEL: sccweqand:
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; CHECK-V1: if r1 == 0
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; CHECK-V2: if r1 == 0
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define i16 @sccwneand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp ne i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK-LABEL: sccwneand:
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; CHECK-V1: if r1 != 0
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; CHECK-V2: if r1 != 0
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define i16 @sccwne(i16 %a, i16 %b) nounwind {
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%t1 = icmp ne i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwne:
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; CHECK-V1: if r1 != r2
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; CHECK-V2: if r1 != r2
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define i16 @sccweq(i16 %a, i16 %b) nounwind {
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%t1 = icmp eq i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccweq:
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; CHECK-V1: if r1 == r2
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; CHECK-V2: if r1 == r2
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define i16 @sccwugt(i16 %a, i16 %b) nounwind {
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%t1 = icmp ugt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwugt:
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; CHECK-V1: if r1 > r2
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; CHECK-V2: if r1 > r2
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define i16 @sccwuge(i16 %a, i16 %b) nounwind {
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%t1 = icmp uge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwuge:
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; CHECK-V1: if r1 >= r2
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; CHECK-V2: if r1 >= r2
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define i16 @sccwult(i16 %a, i16 %b) nounwind {
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%t1 = icmp ult i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwult:
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; CHECK-V1: if r2 > r1
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; CHECK-V2: if r1 < r2
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define i16 @sccwule(i16 %a, i16 %b) nounwind {
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%t1 = icmp ule i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwule:
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; CHECK-V1: if r2 >= r1
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; CHECK-V2: if r1 <= r2
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define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
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%t1 = icmp sgt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwsgt:
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; CHECK-V1: if r1 s> r2
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; CHECK-V2: if r1 s> r2
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define i16 @sccwsge(i16 %a, i16 %b) nounwind {
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%t1 = icmp sge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwsge:
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; CHECK-V1: if r1 s>= r2
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; CHECK-V2: if r1 s>= r2
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define i16 @sccwslt(i16 %a, i16 %b) nounwind {
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%t1 = icmp slt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwslt:
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; CHECK-V1: if r2 s> r1
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; CHECK-V2: if r1 s< r2
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define i16 @sccwsle(i16 %a, i16 %b) nounwind {
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%t1 = icmp sle i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwsle:
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; CHECK-V1: if r2 s>= r1
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; CHECK-V2: if r1 s<= r2
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