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25 lines
620 B
LLVM
25 lines
620 B
LLVM
; RUN: llc -march=hexagon -hexbit-extract=0 < %s | FileCheck %s
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; Make sure we don't generate zxtb to transfer a predicate register into
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; a general purpose register.
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; CHECK: r0 = p0
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; CHECK-NOT: zxtb(p
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; CHECK-NOT: and(p
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; CHECK-NOT: extract(p
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; CHECK-NOT: extractu(p
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target triple = "hexagon"
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; Function Attrs: nounwind
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define i32 @fred() local_unnamed_addr #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.C4.and.and(i32 undef, i32 undef, i32 undef)
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ret i32 %0
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}
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declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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attributes #1 = { nounwind readnone }
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