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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
62 lines
2.6 KiB
LLVM
62 lines
2.6 KiB
LLVM
; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s
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; CHECK-LABEL: V6_vgathermw
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; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
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; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
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; CHECK-LABEL: V6_vgathermh
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; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
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; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
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; CHECK-LABEL: V6_vgathermhw
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; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h
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; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
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; CHECK-LABEL: V6_vgathermwq
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; CHECK: if (q{{[0-3]+}}) vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
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; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
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; CHECK-LABEL: V6_vgathermhq
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; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
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; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
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; CHECK-LABEL: V6_vgathermhwq
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; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h
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; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
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declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
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declare void @llvm.hexagon.V6.vgathermw(i8*, i32, i32, <16 x i32>)
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define void @V6_vgathermw(i8* %a, i32 %b, i32 %c, <16 x i32> %d) {
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call void @llvm.hexagon.V6.vgathermw(i8* %a, i32 %b, i32 %c, <16 x i32> %d)
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ret void
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}
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declare void @llvm.hexagon.V6.vgathermh(i8*, i32, i32, <16 x i32>)
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define void @V6_vgathermh(i8* %a, i32 %b, i32 %c, <16 x i32> %d) {
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call void @llvm.hexagon.V6.vgathermh(i8* %a, i32 %b, i32 %c, <16 x i32> %d)
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ret void
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}
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declare void @llvm.hexagon.V6.vgathermhw(i8*, i32, i32, <32 x i32>)
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define void @V6_vgathermhw(i8* %a, i32 %b, i32 %c, <32 x i32> %d) {
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call void @llvm.hexagon.V6.vgathermhw(i8* %a, i32 %b, i32 %c, <32 x i32> %d)
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ret void
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}
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declare void @llvm.hexagon.V6.vgathermwq(i8*, <64 x i1>, i32, i32, <16 x i32>)
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define void @V6_vgathermwq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <16 x i32> %e) {
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%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
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call void @llvm.hexagon.V6.vgathermwq(i8* %a, <64 x i1> %1, i32 %c, i32 %d, <16 x i32> %e)
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ret void
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}
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declare void @llvm.hexagon.V6.vgathermhq(i8*, <64 x i1>, i32, i32, <16 x i32>)
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define void @V6_vgathermhq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <16 x i32> %e) {
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%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
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call void @llvm.hexagon.V6.vgathermhq(i8* %a, <64 x i1> %1, i32 %c, i32 %d, <16 x i32> %e)
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ret void
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}
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declare void @llvm.hexagon.V6.vgathermhwq(i8*, <64 x i1>, i32, i32, <32 x i32>)
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define void @V6_vgathermhwq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <32 x i32> %e) {
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%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
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call void @llvm.hexagon.V6.vgathermhwq(i8* %a, <64 x i1> %1, i32 %c, i32 %d, <32 x i32> %e)
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ret void
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}
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