..
autohvx
[Hexagon] Fix perfect shuffle generation for single vectors
2020-08-30 06:43:16 -05:00
intrinsics
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
loop-idiom
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
pipeliner
vect
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
64bit_tstbit.ll
abi-padding-2.ll
[Hexagon] Reducing minimum alignment requirement
2020-06-24 10:28:37 -05:00
abi-padding.ll
[Hexagon] Reducing minimum alignment requirement
2020-06-24 10:28:37 -05:00
abs.ll
absaddr-store.ll
absimm.ll
add_int_double.ll
add_mpi_RRR.ll
add-use.ll
addaddi.ll
addasl-address.ll
addh-sext-trunc.ll
addh-shifted.ll
addh.ll
addr-calc-opt.ll
addr-mode-opt.ll
addrmode-align.ll
addrmode-globoff.mir
addrmode-immop.mir
addrmode-indoff.ll
addrmode-keepdeadphis.ll
addrmode-keepdeadphis.mir
addrmode-offset.ll
addrmode-rr-to-io.mir
addrmode.ll
addsubcarry.ll
adjust-latency-stackST.ll
aggr-antidep-tied.ll
aggr-copy-order.ll
aggr-licm.ll
aggressive_licm.ll
align_Os.ll
align_test.ll
alu64.ll
always-ext.ll
anti-dep-partial.mir
args.ll
ashift-left-right.ll
asr-rnd64.ll
asr-rnd.ll
assert-postinc-ptr-not-value.ll
atomic-rmw-add.ll
Handle part-word LL/SC in atomic expansion pass
2020-04-28 10:07:39 -05:00
atomic-store-byte.ll
Align store conditional address
2020-07-30 10:42:00 -05:00
Atomics.ll
avoid-predspill-calleesaved.ll
avoid-predspill.ll
avoidVectorLowering.ll
bank-conflict-load.mir
bank-conflict.mir
barrier-flag.ll
base-offset-addr.ll
base-offset-post.ll
base-offset-stv4.ll
bit-addr-align.mir
bit-bitsplit-at.ll
bit-bitsplit-regclass.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
bit-bitsplit-src.ll
bit-bitsplit.ll
bit-cmp0.mir
bit-eval.ll
bit-ext-sat.ll
bit-extract-off.ll
bit-extract.ll
bit-extractu-half.ll
bit-gen-rseq.ll
bit-has.ll
bit-loop-rc-mismatch.ll
bit-loop.ll
bit-phi.ll
bit-rie.ll
bit-skip-byval.ll
bit-validate-reg.ll
bit-visit-flowq.ll
bitconvert-vector.ll
bitmanip.ll
bkfir.ll
block-addr.ll
block-address.ll
block-ranges-nodef.ll
blockaddr-fpic.ll
branch-folder-hoist-kills.mir
branch-non-mbb.ll
branchfolder-insert-impdef.mir
branchfolder-keep-impdef.ll
BranchPredict.ll
brcond-setne.ll
brev_ld.ll
brev_st.ll
bss-local.ll
bug6757-endloop.ll
bug9049.ll
bug9963.ll
bug14859-iv-cleanup-lpad.ll
bug14859-split-const-block-addr.ll
bug15515-shuffle.ll
bug17276.ll
bug17386.ll
bug18008.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
bug18491-optsize.ll
bug19076.ll
bug19119.ll
bug19254-ifconv-vec.ll
bug27085.ll
bug31839.ll
bug-aa4463-ifconv-vecpred.ll
bug-allocframe-size.ll
bug-hcp-tied-kill.ll
bugAsmHWloop.ll
build-vector-shuffle.ll
build-vector-v4i8-zext.ll
builtin-expect.ll
builtin-prefetch-offset.ll
builtin-prefetch.ll
call-long1.ll
call-ret-i1.ll
call-v4.ll
calling-conv-2.ll
calling-conv.ll
callR_noreturn.ll
callr-dep-edge.ll
cext-check.ll
cext-ice.ll
cext-opt-basic.mir
cext-opt-negative-fi.mir
cext-opt-numops.mir
cext-opt-range-assert.mir
cext-opt-range-offset.mir
Simplify MachineVerifier's block-successor verification.
2020-06-06 22:30:51 -04:00
cext-opt-shifted-range.mir
cext-opt-stack-no-rr.mir
cext-unnamed-global.mir
cext-valid-packet1.ll
cext-valid-packet2.ll
cext.ll
cexti16.ll
cfgopt-fall-through.ll
cfi_offset2.ll
cfi_offset.ll
cfi-late-and-regpressure-init.ll
cfi-late.ll
cfi-offset.ll
check-dot-new.ll
check-subregister-for-latency.ll
Handle cases for subregisters.
2020-04-30 20:32:33 -05:00
checktabs.ll
circ_ld.ll
circ_ldd_bug.ll
circ_ldw.ll
circ_new.ll
circ_pcr_assert.ll
circ_st.ll
circ-load-isel.ll
clr_set_toggle.ll
cmp_pred2.ll
cmp_pred_reg.ll
cmp_pred.ll
cmp-extend.ll
cmp-promote.ll
cmp-to-genreg.ll
cmp-to-predreg.ll
cmp.ll
cmpb_gtu.ll
cmpb_pred.ll
cmpb-dec-imm.ll
cmpb-eq.ll
cmpbeq.ll
cmph-gtu.ll
cmpy-round.ll
coalesce_tfri.ll
coalescing-hvx-across-calls.ll
combine_ir.ll
combine_lh.ll
combine-imm-ext2.ll
combine-imm-ext.ll
combine.ll
combiner-lts.ll
common-gep-basic.ll
common-gep-icm.ll
common-gep-inbounds.ll
common-global-addr.ll
compound.ll
concat-vectors-legalize.ll
const64.ll
const-combine.ll
const-pool-tf.ll
constant_compound.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
constext-call.ll
constext-immstore.ll
constext-replace.ll
constp-andir-global.mir
constp-clb.ll
constp-combine-neg.ll
constp-ctb.ll
constp-extract.ll
constp-physreg.ll
constp-rewrite-branches.ll
constp-rseq.ll
constp-vsplat.ll
convert_const_i1_to_i8.ll
convert-to-dot-old.ll
convertdptoint.ll
convertdptoll.ll
convertsptoint.ll
convertsptoll.ll
copy-to-combine-dbg.ll
count_0s.ll
countbits-basic.ll
csr_stub_calls_dwarf_frame_info.ll
csr-func-usedef.ll
csr-stubs-spill-threshold.ll
ctor.ll
dadd.ll
dag-combine-select-or0.ll
dag-indexed.ll
dccleana.ll
dead-store-stack.ll
dealloc_return.ll
dealloc-store.ll
debug-line_table_start.ll
debug-prologue-loc.ll
debug-prologue.ll
def-undef-deps.ll
default-align.ll
deflate.ll
df-min-max.ll
dfp.ll
dhry_proc8.ll
dhry_stall.ll
dhry.ll
disable-const64-tinycore.ll
disable-const64.ll
dmul.ll
dont_rotate_pregs_at_O2.ll
double.ll
dsub.ll
dualstore.ll
duplex-addi-global-imm.mir
duplex.ll
dwarf-discriminator.ll
early-if-conv-lifetime.mir
early-if-conversion-bug1.ll
early-if-debug.mir
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
early-if-low8.mir
early-if-merge-loop.ll
early-if-phi-i1.ll
early-if-predicator.mir
early-if-spare.ll
early-if-vecpi.ll
early-if-vecpred.ll
early-if.ll
eh_return-r30.ll
eh_return.ll
eh_save_restore.ll
ehabi.ll
eliminate-pred-spill.ll
entryBB-isLoopHdr.ll
expand-condsets-basic.ll
expand-condsets-copy-lis.ll
expand-condsets-dead-bad.ll
expand-condsets-dead-pred.ll
expand-condsets-dead.ll
expand-condsets-def-undef.mir
expand-condsets-extend.ll
expand-condsets-imm.mir
expand-condsets-impuse2.mir
expand-condsets-impuse.mir
expand-condsets-phys-reg.mir
expand-condsets-pred-undef2.ll
expand-condsets-pred-undef.ll
expand-condsets-rm-reg.mir
expand-condsets-rm-segment.ll
expand-condsets-same-inputs.mir
expand-condsets-undef2.ll
expand-condsets-undef.ll
expand-condsets-undefvni.ll
expand-condsets.ll
expand-copyw-undef.mir
expand-vselect-kill.mir
expand-vstorerw-undef2.ll
expand-vstorerw-undef.ll
expand-wselect.mir
extload-combine.ll
extlow.ll
extract_0bits.ll
extract-basic.ll
extractu_0bits.ll
fadd.ll
fcmp.ll
feature-compound.ll
feature-memops.ll
find-loop-instr.ll
find-loop.ll
fixed-spill-mutable.ll
float-amode.ll
float-bitcast.ll
float-const64-G0.ll
float-gen-cmpop.ll
float.ll
floatconvert-ieee-rnd-near.ll
fltnvjump.ll
fmadd.ll
fminmax-v67.ll
fminmax.ll
fmul-v67.ll
fmul.ll
formal-args-i1.ll
fp_latency.ll
fpelim-basic.ll
frame-offset-overflow.ll
fsel.ll
fsub.ll
funnel-shift2.ll
[Hexagon] Correct the order of operands when lowering funnel shift-left
2020-07-28 21:22:41 -05:00
funnel-shift.ll
[Hexagon] Correct the order of operands when lowering funnel shift-left
2020-07-28 21:22:41 -05:00
fusedandshift.ll
generic-cpu.ll
getBlockAddress.ll
glob-align-volatile.ll
global64bitbug.ll
global-const-gep.ll
global-ctor-pcrel.ll
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll
Halide_vec_cast_trunc1.ll
Halide_vec_cast_trunc2.ll
hasfp-crash1.ll
hasfp-crash2.ll
hello-world-v55.ll
hello-world-v60.ll
hexagon_cfi_offset.ll
hexagon_vector_loop_carried_reuse_commutative.ll
hexagon_vector_loop_carried_reuse_constant.ll
hexagon_vector_loop_carried_reuse_invalid.ll
hexagon_vector_loop_carried_reuse.ll
hexagon-cond-jumpr31.ll
hexagon-tfr-add.ll
hexagon-verify-implicit-use.ll
hidden-relocation.ll
honor-optsize.ll
hrc-stack-coloring.ll
hvx-bitcast-v64i1.ll
[Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX
2020-08-26 13:10:22 -05:00
hvx-byte-store-double.ll
hvx-byte-store.ll
hvx-dbl-dual-output.ll
hvx-double-vzero.ll
hvx-dual-output.ll
hvx-isel-vselect-v256i16.ll
[Hexagon] Check if EVT is simple type in HVX lowering
2020-08-25 15:02:44 -05:00
hvx-loopidiom-memcpy.ll
hvx-nontemporal.ll
hvx-vzero.ll
hwloop1.ll
hwloop2.ll
hwloop3.ll
hwloop4.ll
hwloop5.ll
hwloop-cleanup.ll
hwloop-const.ll
hwloop-crit-edge.ll
hwloop-dbg.ll
hwloop-ice.ll
hwloop-le.ll
hwloop-long.ll
hwloop-loop1.ll
hwloop-lt1.ll
hwloop-lt.ll
hwloop-missed.ll
hwloop-ne.ll
hwloop-noreturn-call.ll
hwloop-ph-deadcode.ll
hwloop-phi-subreg.ll
hwloop-pos-ivbump1.ll
hwloop-preh.ll
hwloop-preheader.ll
hwloop-range.ll
hwloop-recursion.ll
hwloop-redef-imm.mir
hwloop-subreg.ll
hwloop-swap.ll
hwloop-with-return-call.ll
hwloop-wrap2.ll
hwloop-wrap.ll
hx_V6_lo_hi.ll
i1_VarArg.ll
i8_VarArg.ll
i16_VarArg.ll
i128-bitop.ll
idxload-with-zero-offset.ll
ifcvt-common-kill.mir
ifcvt-diamond-bad.ll
ifcvt-diamond-bug-2016-08-26.ll
ifcvt-diamond-ret.mir
ifcvt-edge-weight.ll
[llc] (almost) remove --print-machineinstrs
2020-07-20 10:43:28 -07:00
ifcvt-impuse-livein.mir
ifcvt-live-subreg.mir
ifcvt-simple-bprob.ll
ignore-terminal-mbb.ll
indirect-br.ll
initial-exec.ll
inline-asm-a.ll
inline-asm-bad-constraint.ll
inline-asm-clobber-lr.ll
inline-asm-error.ll
inline-asm-filetype-null.ll
inline-asm-hexagon.ll
inline-asm-i1.ll
inline-asm-qv.ll
inline-asm-vecpred128.ll
inlineasm-output-template.ll
insert4.ll
insert-basic.ll
insert.ll
intrinsics-v60-alu.ll
intrinsics-v60-misc.ll
intrinsics-v60-permute.ll
intrinsics-v60-shift.ll
intrinsics-v60-vcmp.ll
intrinsics-v60-vmpy-acc-128B.ll
intrinsics-v60-vmpy-acc.ll
intrinsics-v60-vmpy.ll
intrinsics-v66.ll
intrinsics-v67.ll
invalid-dotnew-attempt.mir
invalid-memrefs.ll
is-legal-void.ll
isel-bitcast-v8i1-i8.ll
isel-bitcast-v8i8-v4i16.ll
isel-combine-half.ll
isel-dcfetch-intrin-map.ll
isel-exti1.ll
isel-global-offset-alignment.ll
isel-hvx-pred-bitcast-order.ll
[Hexagon] Fix perfect shuffle generation for single vectors
2020-08-30 06:43:16 -05:00
isel-i1arg-crash.ll
isel-minmax-v64bit.ll
isel-op-zext-i1.ll
isel-prefer.ll
isel-select-v4i8.ll
isel-setcc-i1.ll
isel-simplify-crash.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
isel-uaddo-1.ll
isel-vacopy.ll
isel-vlsr-v2i16.ll
isel-vselect-v4i8.ll
isel-zext-vNi1.ll
jt-in-text.ll
jump-prob.ll
jump-table-g0.ll
jump-table-isel.ll
large-number-of-preds.ll
late_instr.ll
late-pred.ll
lcomm.ll
lit.local.cfg
livephysregs-add-pristines.mir
livephysregs-lane-masks2.mir
[Hexagon] Add missing live-in registers in some codegen tests
2020-04-23 10:28:04 -05:00
livephysregs-lane-masks.mir
[Hexagon] Add missing live-in registers in some codegen tests
2020-04-23 10:28:04 -05:00
livephysregs-regmask-clobber.mir
load-abs.ll
loadi1-G0.ll
loadi1-v4-G0.ll
loadi1-v4.ll
loadi1.ll
local-exec.ll
long-calls.ll
loop_correctness.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
loop-prefetch.ll
loop-rotate-bug.ll
loop-rotate-liveins.ll
lower-extract-subvector.ll
lower-i1.ll
lsr-post-inc-cross-use-offsets.ll
lsr-postinc-nested-loop.ll
M4_mpyri_addi_global.ll
M4_mpyrr_addi_global.ll
machine-cp-clobbers.mir
machine-sink.ll
macint.ll
maddsubu.ll
mapped_intrinsics.ll
maxd.ll
maxh.ll
maxud.ll
maxuw.ll
maxw.ll
mem-fi-add.ll
mem-load-circ.ll
mem-ops-sub_01.ll
mem-ops-sub_i16_01.ll
mem-ops-sub_i16.ll
mem-ops-sub.ll
memcmp.ll
memcpy-likely-aligned.ll
memcpy-memmove-inline.ll
memop-bit18.ll
memops1.ll
memops2.ll
memops3.ll
memops_global.ll
memops-stack.ll
memops.ll
memset-inline.ll
mind.ll
minu-zext-8.ll
minu-zext-16.ll
minud.ll
minuw.ll
minw.ll
mipi-double-small.ll
misaligned_double_vector_store_not_fast.ll
misaligned-access.ll
misaligned-const-load.ll
misaligned-const-store.ll
misched-top-rptracker-sync.ll
mlong-calls.ll
mnaci_v66.ll
mpy.ll
mpysin-imm.ll
mul64-sext.ll
mul64.ll
mulh.ll
mulhs.ll
multi-cycle.ll
mux-basic.ll
mux-kill1.mir
mux-kill2.mir
mux-kill3.mir
mux-undef.ll
muxii-bug.ll
muxii-crash.ll
namedreg.ll
neg.ll
newify-crash.ll
newvaluejump2.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
newvaluejump3.ll
newvaluejump-c4.mir
newvaluejump-float.mir
newvaluejump-kill2.mir
newvaluejump-kill.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
newvaluejump-postinc.ll
newvaluejump-solo.mir
newvaluejump.ll
newvalueSameReg.ll
newvaluestore2.ll
newvaluestore.ll
no_struct_element.ll
no-falign-function-for-size.ll
no-packets-gather.ll
no-packets.ll
noFalignAfterCallAtO2.ll
noreturn-noepilog.ll
noreturn-notail.ll
noreturn-stack-elim.ll
not-op.ll
ntstbit.ll
nv_store_vec.ll
NVJumpCmp.ll
opt-addr-mode-subreg-use.ll
opt-addr-mode.ll
opt-fabs.ll
opt-fneg.ll
opt-glob-addrs-000.ll
opt-glob-addrs-001.ll
opt-glob-addrs-003.ll
opt-sext-intrinsics.ll
opt-spill-volatile.ll
optimize-mux.ll
P08214.ll
packed-store.ll
packetize_cond_inst.ll
packetize-allocframe.ll
packetize-call-r29.ll
packetize-cfi-location.ll
packetize-dccleana.mir
packetize-debug-loc.mir
packetize-frame-setup-destroy.mir
packetize-impdef-1.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
packetize-impdef.ll
packetize-l2fetch.ll
packetize-load-store-aliasing.mir
packetize-nvj-no-prune.mir
packetize-nvstore.mir
packetize-return-arg.ll
packetize-tailcall-arg.ll
packetize-update-offset.mir
packetize-vgather-slot01.mir
packetize-volatiles.ll
packetizer-resources.ll
partword-cmpxchg.ll
Handle part-word LL/SC in atomic expansion pass
2020-04-28 10:07:39 -05:00
peephole-kill-flags.ll
peephole-move-phi.ll
peephole-op-swap.ll
phi-elim.ll
pic-jt-big.ll
pic-jumptables.ll
pic-local.ll
pic-regusage.ll
pic-sdata.ll
pic-simple.ll
pic-static.ll
plt-rel.ll
pmpyw_acc.ll
post-inc-aa-metadata.ll
post-ra-kill-update.mir
postinc-aggr-dag-cycle.ll
postinc-baseoffset.mir
postinc-float.ll
postinc-load.ll
postinc-offset.ll
postinc-order.ll
postinc-store.ll
postra-sink-subregs.mir
PR33749.ll
pred-absolute-store.ll
pred-gp.ll
pred-instrs.ll
pred-sched.ll
pred-simp.ll
pred-taken-jump.ll
predicate-copy.ll
predicate-logical.ll
predicate-rcmp.ll
predtfrs.ll
prefetch-intr.ll
prefetch-shuffler-ice.ll
prob-types.ll
prof-early-if.ll
Revert "Include static prof data when collecting loop BBs"
2020-03-24 09:41:16 -07:00
propagate-vcombine.ll
ps_call_nr.ll
rdf-copy-renamable-reserved.mir
rdf-copy-undef2.ll
rdf-copy-undef.ll
rdf-copy.ll
rdf-cover-use.ll
rdf-dead-loop.ll
rdf-def-mask.ll
rdf-ehlabel-live.mir
rdf-extra-livein.ll
rdf-filter-defs.ll
rdf-ignore-undef.ll
rdf-inline-asm-fixed.ll
rdf-inline-asm.ll
rdf-kill-last-op.ll
rdf-multiple-phis-up.ll
rdf-phi-shadows.ll
rdf-phi-up.ll
rdf-reset-kills.ll
readcyclecounter.ll
redundant-branching2.ll
reg_seq.ll
reg-by-name.ll
reg-eq-cmp.ll
reg-scav-imp-use-dbl-vec.ll
reg-scavengebug-2.ll
reg-scavengebug-3.ll
reg-scavengebug-4.ll
reg-scavengebug-5.ll
reg-scavengebug.ll
reg-scavenger-valid-slot.ll
regalloc-bad-undef.mir
regalloc-block-overlap.ll
regalloc-coal-extend-short-subrange.mir
[RegisterCoalescer] Extend a subrange if needed when filling range gap
2020-05-04 16:49:59 -05:00
regalloc-coal-fullreg-undef.mir
regalloc-liveout-undef.mir
registerscav-missing-spill-slot.ll
registerscavenger-fail1.ll
regp-underflow.ll
regscav-wrong-super-sub-regs.ll
regscavenger_fail_hwloop.ll
regscavengerbug.ll
relax.ll
remove_lsr.ll
remove-endloop.ll
restore-single-reg.ll
ret-struct-by-val.ll
retval-redundant-copy.ll
rotate-multi.ll
rotate.ll
rotl-i64.ll
runtime-stkchk.ll
S3_2op.ll
save-kill-csr.ll
save-regs-thresh.ll
sdata-array.ll
sdata-basic.ll
sdata-expand-const.ll
sdata-explicit-section.ll
sdata-load-size.ll
sdata-opaque-type.ll
sdata-stack-guard.ll
sdiv-minsigned.ll
sdr-basic.ll
sdr-global.mir
sdr-nosplit1.ll
sdr-reg-profit.ll
sdr-shr32.ll
section_7275.ll
select-instr-align.ll
setmemrefs.ll
sf-min-max.ll
sffms.ll
sfmin_dce.ll
sfmpyacc_scale.ll
shrink-frame-basic.ll
signed_immediates.ll
signext-inreg.ll
simple_addend.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
simpletailcall.ll
simplify64bitops_7223.ll
spill-vector-alignment.mir
split-const32-const64.ll
split-muxii.ll
split-vecpred.ll
stack-align1.ll
stack-align2.ll
stack-align-reset.ll
stack-alloca1.ll
stack-alloca2.ll
stack-guard-acceptable-type.ll
static.ll
store1.ll
store_abs.ll
store-abs.ll
store-AbsSet.ll
store-constant.ll
store-imm-amode.ll
store-imm-byte.ll
store-imm-halword.ll
store-imm-large-stack.ll
store-imm-stack-object.ll
store-imm-word.ll
store-shift.ll
store-vector-pred.ll
[Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX
2020-08-26 13:10:22 -05:00
store-widen-aliased-load.ll
store-widen-negv2.ll
store-widen-negv.ll
store-widen-subreg.ll
store-widen.ll
storerd-io-over-rr.ll
storerinewabs.ll
struct_args_large.ll
struct_args.ll
struct_copy_sched_r16.ll
struct_copy.ll
struct-const.ll
sub-add.ll
subh-shifted.ll
subh.ll
subi-asl.ll
SUnit-boundary-prob.ll
switch-lut-explicit-section.ll
switch-lut-function-section.ll
switch-lut-multiple-functions.ll
switch-lut-text-section.ll
swp-art-deps-rec.ll
swp-bad-sched.ll
swp-badorder.ll
swp-carried-1.ll
swp-carried-dep1.mir
swp-carried-dep2.mir
swp-chain-refs.ll
swp-change-dep1.ll
swp-change-dep-cycle.ll
swp-change-dep.ll
swp-change-deps.ll
swp-check-offset.ll
swp-const-tc1.ll
swp-const-tc2.ll
swp-const-tc3.ll
swp-const-tc.ll
swp-conv3x3-nested.ll
swp-copytophi-dag.ll
swp-crash-iter.ll
swp-cse-phi.ll
swp-dag-phi1.ll
swp-dag-phi.ll
swp-dead-regseq.ll
swp-dep-neg-offset.ll
swp-disable-Os.ll
swp-epilog-numphis.ll
swp-epilog-phi2.ll
swp-epilog-phi4.ll
swp-epilog-phi5.ll
swp-epilog-phi6.ll
swp-epilog-phi7.ll
swp-epilog-phi8.ll
swp-epilog-phi9.ll
swp-epilog-phi10.ll
swp-epilog-phi11.ll
swp-epilog-phi12.ll
swp-epilog-phi13.ll
[ModuloSchedule] Fix epilogue peeling with illegal phi.
2020-05-07 10:04:05 -07:00
swp-epilog-reuse2.ll
swp-epilog-reuse3.ll
swp-epilog-reuse4.ll
swp-epilog-reuse-1.ll
swp-epilog-reuse.ll
swp-exit-fixup.ll
swp-fix-last-use1.ll
swp-fix-last-use.ll
swp-intreglow8.ll
swp-kernel-last-use.ll
swp-kernel-phi1.ll
swp-large-rec.ll
swp-listen-loop3.ll
swp-loop-carried-crash.ll
swp-loop-carried-unknown.ll
swp-loop-carried.ll
swp-loopval.ll
swp-lots-deps.ll
swp-matmul-bitext.ll
swp-max-stage3.ll
swp-max.ll
swp-maxstart.ll
swp-memrefs-epilog.ll
swp-more-phi.ll
swp-multi-loops.ll
swp-multi-phi-refs.ll
swp-new-phi.ll
swp-node-order.ll
swp-order1.ll
swp-order-carried.ll
swp-order-copies.ll
swp-order-deps1.ll
swp-order-deps3.ll
swp-order-deps4.ll
swp-order-deps5.ll
swp-order-deps6.ll
swp-order-deps7.ll
swp-order-prec.ll
swp-order.ll
swp-phi-ch-offset.ll
swp-phi-chains.ll
swp-phi-def-use.ll
swp-phi-dep1.ll
swp-phi-dep.ll
swp-phi-order.ll
swp-phi-ref1.ll
swp-phi-ref.ll
swp-phi-start.ll
swp-phi.ll
swp-physreg.ll
swp-pragma-disable-bug.ll
[Pipeliner] Fix the bug in pragma that disables the pipeliner.
2020-04-10 12:52:16 -05:00
swp-pragma-disable.ii
swp-pragma-initiation-interval.ii
swp-prolog-phi4.ll
swp-prolog-phi.ll
swp-regseq.ll
swp-remove-dep-ice.ll
swp-rename-dead-phi.ll
swp-rename.ll
swp-replace-uses1.ll
swp-resmii-1.ll
swp-resmii.ll
swp-reuse-phi-1.ll
swp-reuse-phi-2.ll
swp-reuse-phi-4.ll
swp-reuse-phi-5.ll
swp-reuse-phi-6.ll
swp-reuse-phi.ll
swp-sigma.ll
swp-stages3.ll
swp-stages4.ll
swp-stages5.ll
swp-stages.ll
swp-subreg.ll
swp-swap.ll
swp-tfri.ll
swp-vect-dotprod.ll
swp-vmult.ll
swp-vsum.ll
swp-xxh2.ll
tail-call-mem-intrinsics.ll
tail-call-trunc.ll
tail-dup-subreg-abort.ll
tail-dup-subreg-map.ll
tailcall_fastcc_ccc.ll
target-flag-ext.mir
tc_duplex_asm.ll
tc_duplex.ll
tc_sched1.ll
tc_sched.ll
tcm-zext.ll
testbits.ll
tfr-cleanup.ll
tfr-mux-nvj.ll
tfr-to-combine.ll
tied_oper.ll
tiny_bkfir_artdeps.ll
tiny_bkfir_loop_align.ll
tinycore.ll
tls_gd.ll
tls_pic.ll
tls_static.ll
trap-crash.ll
trap-unreachable.ll
trivialmemaliascheck.ll
trunc-mpy.ll
tstbit.ll
two-addr-tied-subregs.mir
two-crash.ll
twoaddressbug.ll
undef-ret.ll
undo-dag-shift.ll
union-1.ll
unordered-fcmp.ll
unreachable-mbb-phi-subreg.mir
upper-mpy.ll
usr-ovf-dep.ll
v5_insns.ll
v6-inlasm1.ll
v6-inlasm2.ll
v6-inlasm3.ll
v6-inlasm4.ll
v6-shuffl.ll
v6-spill1.ll
v6-unaligned-spill.ll
v6-vecpred-copy.ll
v6vassignp.ll
v6vec_inc1.ll
v6vec_zero.ll
v6vec-vmemcur-prob.mir
v6vec-vmemu1.ll
v6vec-vmemu2.ll
v6vec-vprint.ll
v6vec-vshuff.ll
v6vect-dbl-fail1.ll
v6vect-dbl-spill.ll
v6vect-dbl.ll
v6vect-dh1.ll
v6vect-locals1.ll
v6vect-no-sideeffects.ll
v6vect-pred2.ll
v6vect-spill-kill.ll
v6vect-vmem1.ll
v6vect-vsplat.ll
v60_Q6_P_rol_PI.ll
v60_sort16.ll
v60-align.ll
v60-cur.ll
v60-haar-postinc.ll
v60-halide-vcombinei8.ll
v60-vec-128b-1.ll
v60-vecpred-spill.ll
v60-vsel1.ll
v60-vsel2.ll
v60Intrins.ll
v60rol-instrs.ll
v60small.ll
[Hexagon] Fix match pattern in a testcase
2020-03-09 09:09:58 -05:00
v60Vasr.ll
v62-CJAllSlots.ll
v62-inlasm4.ll
V60-VDblNew.ll
vacopy.ll
vadd1.ll
vaddh.ll
validate-offset.ll
vararg_align_check.ll
vararg_double_onstack.ll
vararg_named.ll
vararg-deallocate-sp.ll
vararg-formal.ll
vararg-linux-abi.ll
vararg.ll
varargs-memv.ll
vassign-to-combine.ll
vcombine128_to_req_seq.ll
vcombine_subreg.ll
vcombine_to_req_seq.ll
vdmpy-halide-test.ll
vdotprod.ll
vec-align.ll
vec-call-full1.ll
vec-pred-spill1.ll
vec-vararg-align.ll
vecPred2Vec.ll
vect_setcc_v2i16.ll
vect_setcc.ll
vect-any_extend.ll
vect-dbl-post-inc.ll
vect-downscale.ll
vect-regpairs.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
vect-set_cc_v2i32.ll
vect-vd0.ll
vect-zero_extend.ll
vector-align.ll
vector-ext-load.ll
verify-liveness-at-def.mir
verify-sink-code.ll
verify-undef.ll
vextract-basic.mir
vgather-packetize.mir
[Hexagon] Add missing live-in registers in some codegen tests
2020-04-23 10:28:04 -05:00
vload-postinc-sel.ll
vmemu-128.ll
vmpa-halide-test.ll
vpack_eo.ll
vrcmpys.ll
vselect-pseudo.ll
vsplat-ext.ll
vsplat-isel.ll
wcsrtomb.ll
zextloadi1.ll
