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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
64 lines
1.5 KiB
YAML
64 lines
1.5 KiB
YAML
# RUN: llc -march=hexagon -run-pass hwloops %s -o - | FileCheck %s
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# Normally, if the registers holding the induction variable's bounds
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# are redefined inside of the loop's body, the loop cannot be converted
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# to a hardware loop. However, if the redefining instruction is actually
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# loading an immediate value into the register, this conversion is both
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# possible and legal (since the immediate itself will be used in the
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# loop setup in the preheader).
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# CHECK: [[R0:%[0-9]+]]:intregs = A2_tfrsi 1920
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# CHECK: J2_loop0r %bb.1, [[R0]]
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#
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# CHECK: bb.1.b1 (address-taken):
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# CHECK: ENDLOOP0 %bb.1
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--- |
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define void @fred() {
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b0:
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br label %b1
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b1:
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br label %b2
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b2:
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ret void
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}
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...
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---
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name: fred
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tracksRegLiveness: true
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: intregs }
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- { id: 2, class: intregs }
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- { id: 3, class: intregs }
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- { id: 4, class: intregs }
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- { id: 5, class: intregs }
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- { id: 6, class: intregs }
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- { id: 7, class: intregs }
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- { id: 8, class: predregs }
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body: |
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bb.0.b0:
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liveins: $r0
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successors: %bb.1
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%0 = A2_tfrsi 0
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%1 = A2_tfrsi 0
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%2 = COPY $r0
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bb.1.b1:
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successors: %bb.1, %bb.2
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%3 = PHI %0, %bb.0, %6, %bb.1
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%4 = PHI %1, %bb.0, %5, %bb.1
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S4_storerh_rr %2, %4, 0, %3
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%5 = A2_addi %4, 2
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%6 = A2_addi %3, 1
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; This definition of %7 should not prevent conversion to hardware loop.
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%7 = A2_tfrsi 3840
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%8 = C2_cmpeq %5, %7
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J2_jumpf %8, %bb.1, implicit-def $pc
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J2_jump %bb.2, implicit-def $pc
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bb.2.b2:
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...
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