mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
603 lines
22 KiB
LLVM
603 lines
22 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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@l = external global <32 x i32>
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@k = external global <16 x i32>
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@h = external global <16 x i32>
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@n = external global i64
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@m = external global i32
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; CHECK-LABEL: test1:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vrmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b,#1)
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define void @test1(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %a, i32 %b, i32 1)
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store <32 x i32> %0, <32 x i32>* @l, align 128
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ret void
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}
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; CHECK-LABEL: test2:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vrsad(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.ub,#1)
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define void @test2(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vrsadubi(<32 x i32> %a, i32 %b, i32 1)
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store <32 x i32> %0, <32 x i32>* @l, align 128
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ret void
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}
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; CHECK-LABEL: test3:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vrmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.ub,#1)
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define void @test3(<32 x i32> %a, i32 %b) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vrmpyubi(<32 x i32> %a, i32 %b, i32 1)
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store <32 x i32> %0, <32 x i32>* @l, align 128
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ret void
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}
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; CHECK-LABEL: test4:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b,#1)
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define void @test4(<32 x i32> %a, <32 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %a, <32 x i32> %b, i32 %c, i32 1)
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store <32 x i32> %0, <32 x i32>* @l, align 128
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ret void
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}
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; CHECK-LABEL: test5:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vrsad(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.ub,#1)
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define void @test5(<32 x i32> %a, <32 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vrsadubi.acc(<32 x i32> %a, <32 x i32> %b, i32 %c, i32 1)
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store <32 x i32> %0, <32 x i32>* @l, align 128
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ret void
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}
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; CHECK-LABEL: test6:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vrmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.ub,#0)
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define void @test6(<32 x i32> %a, <32 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vrmpyubi.acc(<32 x i32> %a, <32 x i32> %b, i32 %c, i32 0)
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store <32 x i32> %0, <32 x i32>* @l, align 128
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ret void
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}
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; CHECK-LABEL: test7:
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; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
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define void @test7(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test8:
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; CHECK: v{{[0-9]+}} = vlalign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
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define void @test8(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test9:
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; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-9]+}})
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define void @test9(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test10:
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; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-9]+}}):sat
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define void @test10(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test11:
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; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-9]+}}):rnd:sat
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define void @test11(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test12:
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; CHECK: v{{[0-9]+}}.uh = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-9]+}}):sat
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define void @test12(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test13:
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; CHECK: v{{[0-9]+}}.ub = vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-9]+}}):sat
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define void @test13(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test14:
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; CHECK: v{{[0-9]+}}.ub = vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-9]+}}):rnd:sat
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define void @test14(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test15:
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; CHECK: v{{[0-9]+}}.b = vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-9]+}}):rnd:sat
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define void @test15(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vasrhbrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test16:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h |= vunpacko(v{{[0-9]+}}.b)
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define void @test16(<32 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackob(<32 x i32> %a, <16 x i32> %b)
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store <32 x i32> %0, <32 x i32>* @l, align 128
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ret void
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}
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; CHECK-LABEL: test17:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w |= vunpacko(v{{[0-9]+}}.h)
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define void @test17(<32 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32> %a, <16 x i32> %b)
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store <32 x i32> %0, <32 x i32>* @l, align 128
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ret void
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}
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; CHECK-LABEL: test18:
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; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#3)
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define void @test18(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %a, <16 x i32> %b, i32 3)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test19:
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; CHECK: v{{[0-9]+}} = vlalign(v{{[0-9]+}},v{{[0-9]+}},#3)
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define void @test19(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %a, <16 x i32> %b, i32 3)
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store <16 x i32> %0, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test20:
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; CHECK: v{{[0-9]+}} = vmux(q{{[0-3]+}},v{{[0-9]+}},v{{[0-9]+}})
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define void @test20(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %0, <16 x i32> %b, <16 x i32> %c)
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store <16 x i32> %1, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test21:
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; CHECK: q{{[0-3]+}} = and(q{{[0-3]+}},q{{[0-3]+}})
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define void @test21(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
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%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
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%2 = tail call <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1> %0, <64 x i1> %1)
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%3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)
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store <16 x i32> %3, <16 x i32>* @h, align 64
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ret void
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}
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; CHECK-LABEL: test22:
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; CHECK: q{{[0-3]+}} = or(q{{[0-3]+}},q{{[0-3]+}})
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define void @test22(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
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%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
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%2 = tail call <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1> %0, <64 x i1> %1)
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%3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)
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store <16 x i32> %3, <16 x i32>* @h, align 64
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ret void
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}
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; CHECK-LABEL: test23:
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; CHECK: q{{[0-3]+}} = not(q{{[0-3]+}})
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define void @test23(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
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%1 = tail call <64 x i1> @llvm.hexagon.V6.pred.not(<64 x i1> %0)
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%2 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %1, i32 -1)
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store <16 x i32> %2, <16 x i32>* @h, align 64
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ret void
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}
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; CHECK-LABEL: test24:
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; CHECK: q{{[0-3]+}} = xor(q{{[0-3]+}},q{{[0-3]+}})
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define void @test24(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
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%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
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%2 = tail call <64 x i1> @llvm.hexagon.V6.pred.xor(<64 x i1> %0, <64 x i1> %1)
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%3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)
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store <16 x i32> %3, <16 x i32>* @h, align 64
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ret void
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}
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; CHECK-LABEL: test25:
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; CHECK: q{{[0-3]+}} = or(q{{[0-3]+}},!q{{[0-3]+}})
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define void @test25(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
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%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
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%2 = tail call <64 x i1> @llvm.hexagon.V6.pred.or.n(<64 x i1> %0, <64 x i1> %1)
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%3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)
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store <16 x i32> %3, <16 x i32>* @h, align 64
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ret void
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}
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; CHECK-LABEL: test26:
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; CHECK: q{{[0-3]+}} = and(q{{[0-3]+}},!q{{[0-3]+}})
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define void @test26(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
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%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
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%2 = tail call <64 x i1> @llvm.hexagon.V6.pred.and.n(<64 x i1> %0, <64 x i1> %1)
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%3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)
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store <16 x i32> %3, <16 x i32>* @h, align 64
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ret void
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}
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; CHECK-LABEL: test27:
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; CHECK: q{{[0-3]+}} = vcmp.gt(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
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define void @test27(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %a, <16 x i32> %b)
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)
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store <16 x i32> %1, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test28:
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; CHECK: q{{[0-3]+}} = vcmp.gt(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test28(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vgth(<16 x i32> %a, <16 x i32> %b)
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)
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store <16 x i32> %1, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test29:
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; CHECK: q{{[0-3]+}} = vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test29(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.veqh(<16 x i32> %a, <16 x i32> %b)
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)
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store <16 x i32> %1, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test30:
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; CHECK: q{{[0-3]+}} = vcmp.gt(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test30(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <64 x i1> @llvm.hexagon.V6.vgtw(<16 x i32> %a, <16 x i32> %b)
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)
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store <16 x i32> %1, <16 x i32>* @k, align 64
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ret void
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}
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; CHECK-LABEL: test31:
|
|
; CHECK: q{{[0-3]+}} = vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
|
|
define void @test31(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = tail call <64 x i1> @llvm.hexagon.V6.veqw(<16 x i32> %a, <16 x i32> %b)
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)
|
|
store <16 x i32> %1, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test32:
|
|
; CHECK: q{{[0-3]+}} = vcmp.gt(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)
|
|
define void @test32(<16 x i32> %a, <16 x i32> %b) #0 {
|
|
entry:
|
|
%0 = tail call <64 x i1> @llvm.hexagon.V6.vgtuh(<16 x i32> %a, <16 x i32> %b)
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)
|
|
store <16 x i32> %1, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test33:
|
|
; CHECK: v{{[0-9]+}} |= vand(q{{[0-3]+}},r{{[0-9]+}})
|
|
define void @test33(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
|
|
entry:
|
|
%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %a, <64 x i1> %0, i32 %c)
|
|
store <16 x i32> %1, <16 x i32>* @h, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test34:
|
|
; CHECK: q{{[0-3]+}} |= vand(v{{[0-9]+}},r{{[0-9]+}})
|
|
define void @test34(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
|
|
entry:
|
|
%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
|
|
%1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt.acc(<64 x i1> %0, <16 x i32> %b, i32 %c)
|
|
%2 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %1, i32 -1)
|
|
store <16 x i32> %2, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test35:
|
|
; CHECK: v{{[0-9]+}} = vand(q{{[0-3]+}},r{{[0-9]+}})
|
|
define void @test35(<16 x i32> %a, i32 %b) #0 {
|
|
entry:
|
|
%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 %b)
|
|
store <16 x i32> %1, <16 x i32>* @h, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test36:
|
|
; CHECK: q{{[0-3]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
|
|
define void @test36(<16 x i32> %a, i32 %b) #0 {
|
|
entry:
|
|
%0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 %b)
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)
|
|
store <16 x i32> %1, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test37:
|
|
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = rol(r{{[0-9]+}}:{{[0-9]+}},#38)
|
|
define void @test37(i64 %a) #0 {
|
|
entry:
|
|
%0 = tail call i64 @llvm.hexagon.S6.rol.i.p(i64 %a, i32 38)
|
|
store i64 %0, i64* @n, align 8
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test38:
|
|
; CHECK: r{{[0-9]+}}:{{[0-9]+}} += rol(r{{[0-9]+}}:{{[0-9]+}},#36)
|
|
define void @test38(i64 %a, i64 %b) #0 {
|
|
entry:
|
|
%0 = tail call i64 @llvm.hexagon.S6.rol.i.p.acc(i64 %a, i64 %b, i32 36)
|
|
store i64 %0, i64* @n, align 8
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test39:
|
|
; CHECK: r{{[0-9]+}}:{{[0-9]+}} &= rol(r{{[0-9]+}}:{{[0-9]+}},#25)
|
|
define void @test39(i64 %a, i64 %b) #0 {
|
|
entry:
|
|
%0 = tail call i64 @llvm.hexagon.S6.rol.i.p.and(i64 %a, i64 %b, i32 25)
|
|
store i64 %0, i64* @n, align 8
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test40:
|
|
; CHECK: r{{[0-9]+}}:{{[0-9]+}} -= rol(r{{[0-9]+}}:{{[0-9]+}},#20)
|
|
define void @test40(i64 %a, i64 %b) #0 {
|
|
entry:
|
|
%0 = tail call i64 @llvm.hexagon.S6.rol.i.p.nac(i64 %a, i64 %b, i32 20)
|
|
store i64 %0, i64* @n, align 8
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test41:
|
|
; CHECK: r{{[0-9]+}}:{{[0-9]+}} |= rol(r{{[0-9]+}}:{{[0-9]+}},#22)
|
|
define void @test41(i64 %a, i64 %b) #0 {
|
|
entry:
|
|
%0 = tail call i64 @llvm.hexagon.S6.rol.i.p.or(i64 %a, i64 %b, i32 22)
|
|
store i64 %0, i64* @n, align 8
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test42:
|
|
; CHECK: r{{[0-9]+}}:{{[0-9]+}} ^= rol(r{{[0-9]+}}:{{[0-9]+}},#25)
|
|
define void @test42(i64 %a, i64 %b) #0 {
|
|
entry:
|
|
%0 = tail call i64 @llvm.hexagon.S6.rol.i.p.xacc(i64 %a, i64 %b, i32 25)
|
|
store i64 %0, i64* @n, align 8
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test43:
|
|
; CHECK: r{{[0-9]+}} = rol(r{{[0-9]+}},#14)
|
|
define void @test43(i32 %a) #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.S6.rol.i.r(i32 %a, i32 14)
|
|
%conv = sext i32 %0 to i64
|
|
store i64 %conv, i64* @n, align 8
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test44:
|
|
; CHECK: r{{[0-9]+}} += rol(r{{[0-9]+}},#12)
|
|
define void @test44(i32 %a, i32 %b) #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.S6.rol.i.r.acc(i32 %a, i32 %b, i32 12)
|
|
store i32 %0, i32* @m, align 4
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test45:
|
|
; CHECK: r{{[0-9]+}} &= rol(r{{[0-9]+}},#18)
|
|
define void @test45(i32 %a, i32 %b) #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.S6.rol.i.r.and(i32 %a, i32 %b, i32 18)
|
|
store i32 %0, i32* @m, align 4
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test46:
|
|
; CHECK: r{{[0-9]+}} -= rol(r{{[0-9]+}},#31)
|
|
define void @test46(i32 %a, i32 %b) #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.S6.rol.i.r.nac(i32 %a, i32 %b, i32 31)
|
|
store i32 %0, i32* @m, align 4
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test47:
|
|
; CHECK: r{{[0-9]+}} |= rol(r{{[0-9]+}},#30)
|
|
define void @test47(i32 %a, i32 %b) #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.S6.rol.i.r.or(i32 %a, i32 %b, i32 30)
|
|
store i32 %0, i32* @m, align 4
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test48:
|
|
; CHECK: r{{[0-9]+}} ^= rol(r{{[0-9]+}},#31)
|
|
define void @test48(i32 %a, i32 %b) #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.S6.rol.i.r.xacc(i32 %a, i32 %b, i32 31)
|
|
store i32 %0, i32* @m, align 4
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test49:
|
|
; CHECK: r{{[0-9]+}} = vextract(v{{[0-9]+}},r{{[0-9]+}})
|
|
define void @test49(<16 x i32> %a, i32 %b) #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.V6.extractw(<16 x i32> %a, i32 %b)
|
|
store i32 %0, i32* @m, align 4
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test50:
|
|
; CHECK: v{{[0-9]+}} = vsplat(r{{[0-9]+}})
|
|
define void @test50(i32 %a) #0 {
|
|
entry:
|
|
%0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %a)
|
|
store <16 x i32> %0, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test51:
|
|
; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]+}})
|
|
define void @test51(i32 %a) #0 {
|
|
entry:
|
|
%0 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a)
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)
|
|
store <16 x i32> %1, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test52:
|
|
; CHECK: v{{[0-9]+}}.b = vlut32(v{{[0-9]+}}.b,v{{[0-9]+}}.b,r{{[0-9]+}})
|
|
define void @test52(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {
|
|
entry:
|
|
%0 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb(<16 x i32> %a, <16 x i32> %b, i32 %c)
|
|
store <16 x i32> %0, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test53:
|
|
; CHECK: v{{[0-9]+}}.b |= vlut32(v{{[0-9]+}}.b,v{{[0-9]+}}.b,r{{[0-9]+}})
|
|
define void @test53(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, i32 %d) #0 {
|
|
entry:
|
|
%0 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, i32 %d)
|
|
store <16 x i32> %0, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test54:
|
|
; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h |= vlut16(v{{[0-9]+}}.b,v{{[0-9]+}}.h,r{{[0-9]+}})
|
|
define void @test54(<32 x i32> %a, <16 x i32> %b, <16 x i32> %c, i32 %d) #0 {
|
|
entry:
|
|
%0 = tail call <32 x i32> @llvm.hexagon.V6.vlutvwh.oracc(<32 x i32> %a, <16 x i32> %b, <16 x i32> %c, i32 %d)
|
|
store <32 x i32> %0, <32 x i32>* @l, align 128
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test55:
|
|
; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vlut16(v{{[0-9]+}}.b,v{{[0-9]+}}.h,r{{[0-9]+}})
|
|
define void @test55(<16 x i32> %a, <16 x i32> %b, i32 %l) #0 {
|
|
entry:
|
|
%0 = tail call <32 x i32> @llvm.hexagon.V6.vlutvwh(<16 x i32> %a, <16 x i32> %b, i32 %l)
|
|
store <32 x i32> %0, <32 x i32>* @l, align 128
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test56:
|
|
; CHECK: v{{[0-9]+}}.w = vinsert(r{{[0-9]+}})
|
|
define void @test56(i32 %b) #0 {
|
|
entry:
|
|
%0 = load <16 x i32>, <16 x i32>* @k, align 64
|
|
%1 = tail call <16 x i32> @llvm.hexagon.V6.vinsertwr(<16 x i32> %0, i32 %b)
|
|
store <16 x i32> %1, <16 x i32>* @k, align 64
|
|
ret void
|
|
}
|
|
|
|
declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vrsadubi(<32 x i32>, i32, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vrmpyubi(<32 x i32>, i32, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vrsadubi.acc(<32 x i32>, <32 x i32>, i32, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vrmpyubi.acc(<32 x i32>, <32 x i32>, i32, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vasrwhrndsat(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vasrhubrndsat(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vasrhbrndsat(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vunpackob(<32 x i32>, <16 x i32>) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1>, <64 x i1>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1>, <64 x i1>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.pred.not(<64 x i1>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.pred.xor(<64 x i1>, <64 x i1>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.pred.or.n(<64 x i1>, <64 x i1>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.pred.and.n(<64 x i1>, <64 x i1>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32>, <16 x i32>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.vgth(<16 x i32>, <16 x i32>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.veqh(<16 x i32>, <16 x i32>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.vgtw(<16 x i32>, <16 x i32>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.veqw(<16 x i32>, <16 x i32>) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.vgtuh(<16 x i32>, <16 x i32>) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <64 x i1>, i32) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.vandvrt.acc(<64 x i1>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #0
|
|
declare i64 @llvm.hexagon.S6.rol.i.p(i64, i32) #0
|
|
declare i64 @llvm.hexagon.S6.rol.i.p.acc(i64, i64, i32) #0
|
|
declare i64 @llvm.hexagon.S6.rol.i.p.and(i64, i64, i32) #0
|
|
declare i64 @llvm.hexagon.S6.rol.i.p.nac(i64, i64, i32) #0
|
|
declare i64 @llvm.hexagon.S6.rol.i.p.or(i64, i64, i32) #0
|
|
declare i64 @llvm.hexagon.S6.rol.i.p.xacc(i64, i64, i32) #0
|
|
declare i32 @llvm.hexagon.S6.rol.i.r(i32, i32) #0
|
|
declare i32 @llvm.hexagon.S6.rol.i.r.acc(i32, i32, i32) #0
|
|
declare i32 @llvm.hexagon.S6.rol.i.r.and(i32, i32, i32) #0
|
|
declare i32 @llvm.hexagon.S6.rol.i.r.nac(i32, i32, i32) #0
|
|
declare i32 @llvm.hexagon.S6.rol.i.r.or(i32, i32, i32) #0
|
|
declare i32 @llvm.hexagon.S6.rol.i.r.xacc(i32, i32, i32) #0
|
|
declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #0
|
|
declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vlutvvb(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vlutvwh(<16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32>, <16 x i32>, <16 x i32>, i32) #0
|
|
declare <32 x i32> @llvm.hexagon.V6.vlutvwh.oracc(<32 x i32>, <16 x i32>, <16 x i32>, i32) #0
|
|
declare <16 x i32> @llvm.hexagon.V6.vinsertwr(<16 x i32>, i32) #0
|
|
|
|
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
|