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e25a1a8f41
First patch in a series adding MC layer support for the Arm Scalable
Matrix Extension.
This patch adds the following features:
sme, sme-i64, sme-f64
The sme-i64 and sme-f64 flags are for the optional I16I64 and F64F64
features.
If a target supports I16I64 then the following instructions are
implemented:
* 64-bit integer ADDHA and ADDVA variants (D105570).
* SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS
instructions that accumulate 16-bit integer outer products into 64-bit
integer tiles.
If a target supports F64F64 then the FMOPA and FMOPS instructions that
accumulate double-precision floating-point outer products into
double-precision tiles are implemented.
Outer products are implemented in D105571.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06
Reviewed By: CarolineConcatto
Differential Revision: https://reviews.llvm.org/D105569
153 lines
5.1 KiB
C++
153 lines
5.1 KiB
C++
//===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise AArch64 hardware features
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// such as FPU/CPU/ARCH and extension names.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_AARCH64TARGETPARSER_H
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#define LLVM_SUPPORT_AARCH64TARGETPARSER_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/ARMTargetParser.h"
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#include <vector>
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// FIXME:This should be made into class design,to avoid dupplication.
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namespace llvm {
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class Triple;
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namespace AArch64 {
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// Arch extension modifiers for CPUs.
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enum ArchExtKind : uint64_t {
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AEK_INVALID = 0,
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AEK_NONE = 1,
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AEK_CRC = 1 << 1,
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AEK_CRYPTO = 1 << 2,
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AEK_FP = 1 << 3,
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AEK_SIMD = 1 << 4,
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AEK_FP16 = 1 << 5,
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AEK_PROFILE = 1 << 6,
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AEK_RAS = 1 << 7,
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AEK_LSE = 1 << 8,
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AEK_SVE = 1 << 9,
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AEK_DOTPROD = 1 << 10,
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AEK_RCPC = 1 << 11,
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AEK_RDM = 1 << 12,
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AEK_SM4 = 1 << 13,
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AEK_SHA3 = 1 << 14,
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AEK_SHA2 = 1 << 15,
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AEK_AES = 1 << 16,
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AEK_FP16FML = 1 << 17,
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AEK_RAND = 1 << 18,
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AEK_MTE = 1 << 19,
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AEK_SSBS = 1 << 20,
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AEK_SB = 1 << 21,
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AEK_PREDRES = 1 << 22,
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AEK_SVE2 = 1 << 23,
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AEK_SVE2AES = 1 << 24,
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AEK_SVE2SM4 = 1 << 25,
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AEK_SVE2SHA3 = 1 << 26,
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AEK_SVE2BITPERM = 1 << 27,
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AEK_TME = 1 << 28,
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AEK_BF16 = 1 << 29,
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AEK_I8MM = 1 << 30,
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AEK_F32MM = 1ULL << 31,
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AEK_F64MM = 1ULL << 32,
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AEK_LS64 = 1ULL << 33,
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AEK_BRBE = 1ULL << 34,
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AEK_PAUTH = 1ULL << 35,
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AEK_FLAGM = 1ULL << 36,
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AEK_SME = 1ULL << 37,
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AEK_SMEF64 = 1ULL << 38,
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AEK_SMEI64 = 1ULL << 39,
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};
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enum class ArchKind {
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#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
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#include "AArch64TargetParser.def"
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};
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const ARM::ArchNames<ArchKind> AArch64ARCHNames[] = {
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#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, \
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ARCH_BASE_EXT) \
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{NAME, \
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sizeof(NAME) - 1, \
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CPU_ATTR, \
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sizeof(CPU_ATTR) - 1, \
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SUB_ARCH, \
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sizeof(SUB_ARCH) - 1, \
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ARM::FPUKind::ARCH_FPU, \
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ARCH_BASE_EXT, \
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AArch64::ArchKind::ID, \
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ARCH_ATTR},
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#include "AArch64TargetParser.def"
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};
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const ARM::ExtName AArch64ARCHExtNames[] = {
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#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
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{NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE},
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#include "AArch64TargetParser.def"
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};
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const ARM::CpuNames<ArchKind> AArch64CPUNames[] = {
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#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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{NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
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#include "AArch64TargetParser.def"
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};
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const ArchKind ArchKinds[] = {
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#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \
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ArchKind::ID,
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#include "AArch64TargetParser.def"
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};
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// FIXME: These should be moved to TargetTuple once it exists
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bool getExtensionFeatures(uint64_t Extensions,
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std::vector<StringRef> &Features);
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bool getArchFeatures(ArchKind AK, std::vector<StringRef> &Features);
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StringRef getArchName(ArchKind AK);
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unsigned getArchAttr(ArchKind AK);
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StringRef getCPUAttr(ArchKind AK);
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StringRef getSubArch(ArchKind AK);
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StringRef getArchExtName(unsigned ArchExtKind);
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StringRef getArchExtFeature(StringRef ArchExt);
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// Information by Name
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unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
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uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK);
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StringRef getDefaultCPU(StringRef Arch);
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ArchKind getCPUArchKind(StringRef CPU);
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// Parser
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ArchKind parseArch(StringRef Arch);
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ArchExtKind parseArchExt(StringRef ArchExt);
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ArchKind parseCPUArch(StringRef CPU);
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// Used by target parser tests
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
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bool isX18ReservedByDefault(const Triple &TT);
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struct ParsedBranchProtection {
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StringRef Scope;
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StringRef Key;
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bool BranchTargetEnforcement;
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};
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bool parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP,
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StringRef &Err);
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} // namespace AArch64
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} // namespace llvm
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#endif
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