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74be1319be
AMDGPU normally spills SGPRs to VGPRs. Previously, since all register classes are handled at the same time, this was problematic. We don't know ahead of time how many registers will be needed to be reserved to handle the spilling. If no VGPRs were left for spilling, we would have to try to spill to memory. If the spilled SGPRs were required for exec mask manipulation, it is highly problematic because the lanes active at the point of spill are not necessarily the same as at the restore point. Avoid this problem by fully allocating SGPRs in a separate regalloc run from VGPRs. This way we know the exact number of VGPRs needed, and can reserve them for a second run. This fixes the most serious issues, but it is still possible using inline asm to make all VGPRs unavailable. Start erroring in the case where we ever would require memory for an SGPR spill. This is implemented by giving each regalloc pass a callback which reports if a register class should be handled or not. A few passes need some small changes to deal with leftover virtual registers. In the AMDGPU implementation, a new pass is introduced to take the place of PrologEpilogInserter for SGPR spills emitted during the first run. One disadvantage of this is currently StackSlotColoring is no longer used for SGPR spills. It would need to be run again, which will require more work. Error if the standard -regalloc option is used. Introduce new separate -sgpr-regalloc and -vgpr-regalloc flags, so the two runs can be controlled individually. PBQB is not currently supported, so this also prevents using the unhandled allocator.
196 lines
7.0 KiB
C++
196 lines
7.0 KiB
C++
//===- RegAllocBase.cpp - Register Allocator Base Class -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RegAllocBase class which provides common functionality
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// for LiveIntervalUnion-based register allocators.
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//
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//===----------------------------------------------------------------------===//
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#include "RegAllocBase.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveRegMatrix.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Spiller.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Timer.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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STATISTIC(NumNewQueued, "Number of new live ranges queued");
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// Temporary verification option until we can put verification inside
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// MachineVerifier.
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static cl::opt<bool, true>
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VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
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cl::Hidden, cl::desc("Verify during register allocation"));
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const char RegAllocBase::TimerGroupName[] = "regalloc";
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const char RegAllocBase::TimerGroupDescription[] = "Register Allocation";
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bool RegAllocBase::VerifyEnabled = false;
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//===----------------------------------------------------------------------===//
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// RegAllocBase Implementation
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//===----------------------------------------------------------------------===//
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// Pin the vtable to this file.
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void RegAllocBase::anchor() {}
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void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
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LiveRegMatrix &mat) {
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TRI = &vrm.getTargetRegInfo();
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MRI = &vrm.getRegInfo();
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VRM = &vrm;
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LIS = &lis;
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Matrix = &mat;
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MRI->freezeReservedRegs(vrm.getMachineFunction());
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RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
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}
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// Visit all the live registers. If they are already assigned to a physical
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// register, unify them with the corresponding LiveIntervalUnion, otherwise push
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// them on the priority queue for later assignment.
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void RegAllocBase::seedLiveRegs() {
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NamedRegionTimer T("seed", "Seed Live Regs", TimerGroupName,
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TimerGroupDescription, TimePassesIsEnabled);
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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Register Reg = Register::index2VirtReg(i);
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if (MRI->reg_nodbg_empty(Reg))
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continue;
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enqueue(&LIS->getInterval(Reg));
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}
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}
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// Top-level driver to manage the queue of unassigned VirtRegs and call the
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// selectOrSplit implementation.
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void RegAllocBase::allocatePhysRegs() {
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seedLiveRegs();
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// Continue assigning vregs one at a time to available physical registers.
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while (LiveInterval *VirtReg = dequeue()) {
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assert(!VRM->hasPhys(VirtReg->reg()) && "Register already assigned");
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// Unused registers can appear when the spiller coalesces snippets.
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if (MRI->reg_nodbg_empty(VirtReg->reg())) {
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LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
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aboutToRemoveInterval(*VirtReg);
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LIS->removeInterval(VirtReg->reg());
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continue;
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}
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// Invalidate all interference queries, live ranges could have changed.
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Matrix->invalidateVirtRegs();
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// selectOrSplit requests the allocator to return an available physical
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// register if possible and populate a list of new live intervals that
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// result from splitting.
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LLVM_DEBUG(dbgs() << "\nselectOrSplit "
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<< TRI->getRegClassName(MRI->getRegClass(VirtReg->reg()))
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<< ':' << *VirtReg << " w=" << VirtReg->weight() << '\n');
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using VirtRegVec = SmallVector<Register, 4>;
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VirtRegVec SplitVRegs;
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MCRegister AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
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if (AvailablePhysReg == ~0u) {
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// selectOrSplit failed to find a register!
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// Probably caused by an inline asm.
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MachineInstr *MI = nullptr;
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for (MachineRegisterInfo::reg_instr_iterator
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I = MRI->reg_instr_begin(VirtReg->reg()),
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E = MRI->reg_instr_end();
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I != E;) {
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MI = &*(I++);
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if (MI->isInlineAsm())
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break;
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}
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const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg());
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ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC);
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if (AllocOrder.empty())
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report_fatal_error("no registers from class available to allocate");
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else if (MI && MI->isInlineAsm()) {
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MI->emitError("inline assembly requires more registers than available");
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} else if (MI) {
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LLVMContext &Context =
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MI->getParent()->getParent()->getMMI().getModule()->getContext();
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Context.emitError("ran out of registers during register allocation");
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} else {
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report_fatal_error("ran out of registers during register allocation");
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}
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// Keep going after reporting the error.
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VRM->assignVirt2Phys(VirtReg->reg(), AllocOrder.front());
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continue;
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}
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if (AvailablePhysReg)
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Matrix->assign(*VirtReg, AvailablePhysReg);
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for (Register Reg : SplitVRegs) {
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assert(LIS->hasInterval(Reg));
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LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);
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assert(!VRM->hasPhys(SplitVirtReg->reg()) && "Register already assigned");
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if (MRI->reg_nodbg_empty(SplitVirtReg->reg())) {
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assert(SplitVirtReg->empty() && "Non-empty but used interval");
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LLVM_DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
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aboutToRemoveInterval(*SplitVirtReg);
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LIS->removeInterval(SplitVirtReg->reg());
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continue;
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}
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LLVM_DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
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assert(Register::isVirtualRegister(SplitVirtReg->reg()) &&
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"expect split value in virtual register");
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enqueue(SplitVirtReg);
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++NumNewQueued;
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}
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}
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}
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void RegAllocBase::postOptimization() {
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spiller().postOptimization();
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for (auto DeadInst : DeadRemats) {
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LIS->RemoveMachineInstrFromMaps(*DeadInst);
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DeadInst->eraseFromParent();
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}
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DeadRemats.clear();
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}
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void RegAllocBase::enqueue(LiveInterval *LI) {
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const Register Reg = LI->reg();
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assert(Reg.isVirtual() && "Can only enqueue virtual registers");
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if (VRM->hasPhys(Reg))
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return;
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const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
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if (ShouldAllocateClass(*TRI, RC)) {
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LLVM_DEBUG(dbgs() << "Enqueuing " << printReg(Reg, TRI) << '\n');
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enqueueImpl(LI);
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} else {
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LLVM_DEBUG(dbgs() << "Not enqueueing " << printReg(Reg, TRI)
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<< " in skipped register class\n");
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}
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}
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