Matt Arsenault c1e5a01132 GlobalISel: Lower funnel shifts		2021-03-23 09:11:17 -04:00
..
AArch64	[IR][SVE] Add new llvm.experimental.stepvector intrinsic	2021-03-23 10:43:35 +00:00
AMDGPU	GlobalISel: Lower funnel shifts	2021-03-23 09:11:17 -04:00
ARC
ARM
AVR
BPF
Generic	Temporarily revert "[lli] Make -jit-kind=orc the default JIT engine"	2021-03-23 12:01:30 +01:00
Hexagon
Inputs
Lanai
M68k
Mips
MIR
MSP430
NVPTX
PowerPC
RISCV	[RISCV] Optimize all-constant mask BUILD_VECTORs	2021-03-23 10:11:19 +00:00
SPARC
SystemZ
Thumb
Thumb2	[ARM] Handle debug instrs in ARM Low Overhead Loop pass	2021-03-23 11:49:06 +00:00
VE
WebAssembly
WinCFGuard
WinEH
X86	[X86][AVX] Narrow VPBROADCASTQ->VPBROADCASTD if we don't need the upper bits.	2021-03-23 09:41:02 +00:00
XCore