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b856ac92dc
Summary: Follow up to [x32] "Use ebp/esp as frame and stack pointer": http://reviews.llvm.org/D4617 In that earlier patch, NaCl64 was made to always use rbp. That's needed for most cases because rbp should hold a full 64-bit address within the NaCl sandbox so that load/stores off of rbp don't require sandbox adjustment (zeroing the top 32-bits, then filling those by adding r15). However, llvm.frameaddress returns a pointer and pointers are 32-bit for NaCl64. In this case, use ebp instead, which will make the register copy type check. A similar mechanism may be needed for llvm.eh.return, but is not added in this change. Test Plan: test/CodeGen/X86/frameaddr.ll Reviewers: dschuff, nadav Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D6514 llvm-svn: 223510
71 lines
2.5 KiB
LLVM
71 lines
2.5 KiB
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
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; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-32
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; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
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; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-64
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; RUN: llc < %s -mtriple=x86_64-gnux32 | FileCheck %s --check-prefix=CHECK-X32ABI
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; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-X32ABI
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; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=CHECK-NACL64
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; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-NACL64
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define i8* @test1() nounwind {
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entry:
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; CHECK-32-LABEL: test1
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; CHECK-32: push
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; CHECK-32-NEXT: movl %esp, %ebp
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; CHECK-32-NEXT: movl %ebp, %eax
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; CHECK-32-NEXT: pop
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; CHECK-32-NEXT: ret
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; CHECK-64-LABEL: test1
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; CHECK-64: push
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; CHECK-64-NEXT: movq %rsp, %rbp
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; CHECK-64-NEXT: movq %rbp, %rax
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; CHECK-64-NEXT: pop
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; CHECK-64-NEXT: ret
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; CHECK-X32ABI-LABEL: test1
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; CHECK-X32ABI: pushq %rbp
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; CHECK-X32ABI-NEXT: movl %esp, %ebp
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; CHECK-X32ABI-NEXT: movl %ebp, %eax
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; CHECK-X32ABI-NEXT: popq %rbp
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; CHECK-X32ABI-NEXT: ret
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; CHECK-NACL64-LABEL: test1
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; CHECK-NACL64: pushq %rbp
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; CHECK-NACL64-NEXT: movq %rsp, %rbp
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; CHECK-NACL64-NEXT: movl %ebp, %eax
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%0 = tail call i8* @llvm.frameaddress(i32 0)
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ret i8* %0
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}
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define i8* @test2() nounwind {
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entry:
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; CHECK-32-LABEL: test2
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; CHECK-32: push
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; CHECK-32-NEXT: movl %esp, %ebp
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; CHECK-32-NEXT: movl (%ebp), %eax
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; CHECK-32-NEXT: movl (%eax), %eax
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; CHECK-32-NEXT: pop
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; CHECK-32-NEXT: ret
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; CHECK-64-LABEL: test2
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; CHECK-64: push
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; CHECK-64-NEXT: movq %rsp, %rbp
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; CHECK-64-NEXT: movq (%rbp), %rax
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; CHECK-64-NEXT: movq (%rax), %rax
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; CHECK-64-NEXT: pop
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; CHECK-64-NEXT: ret
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; CHECK-X32ABI-LABEL: test2
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; CHECK-X32ABI: pushq %rbp
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; CHECK-X32ABI-NEXT: movl %esp, %ebp
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; CHECK-X32ABI-NEXT: movl (%ebp), %eax
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; CHECK-X32ABI-NEXT: movl (%eax), %eax
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; CHECK-X32ABI-NEXT: popq %rbp
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; CHECK-X32ABI-NEXT: ret
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; CHECK-NACL64-LABEL: test2
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; CHECK-NACL64: pushq %rbp
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; CHECK-NACL64-NEXT: movq %rsp, %rbp
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; CHECK-NACL64-NEXT: movl (%ebp), %eax
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; CHECK-NACL64-NEXT: movl (%eax), %eax
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%0 = tail call i8* @llvm.frameaddress(i32 2)
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ret i8* %0
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}
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declare i8* @llvm.frameaddress(i32) nounwind readnone
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