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c168815f4b
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
27 lines
1.0 KiB
LLVM
27 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s
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declare float @llvm.powi.f32(float %Val, i32 %power)
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declare double @llvm.powi.f64(double %Val, i32 %power)
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define float @foo_pow_f32(float %y, i32 %p) {
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%1 = tail call float @llvm.powi.f32(float %y, i32 %p)
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; CHECK-NOT: .ent __call_stub_fp_llvm.powi.f32
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; CHECK-NOT: {{.*}} jal llvm.powi.f32
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ret float %1
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}
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define double @foo_pow_f64(double %y, i32 %p) {
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%1 = tail call double @llvm.powi.f64(double %y, i32 %p)
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; CHECK-NOT: .ent __call_stub_fp_llvm.powi.f64
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; CHECK-NOT: {{.*}} jal llvm.powi.f64
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ret double %1
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}
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attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
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attributes #1 = { nounwind readonly }
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!0 = !{!"double", !1}
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!1 = !{!"omnipotent char", !2}
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!2 = !{!"Simple C/C++ TBAA"}
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!3 = !{!"int", !1}
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