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ef6658d2e0
The pipeliner is asserting because the serialization step that occurs at the end is deleting an instruction. The assert occurs later on because there is a use without a definition. The problem occurs when an instruction defines a value used by a REQ_SEQUENCE and that value is used by a COPY instruction. The latencies between these instructions are zero, so they are put in to the same packet. The serialization code is unable to handle this correctly, and ends up putting the REG_SEQUENCE before its definition. There is special code in the serialization step that attempts to handle zero-cost instructions (phis, copy, reg_sequence) differently than regular instructions. Unfortunately, this means the order does not come out correct. This patch simplifies the code by changing the seperate steps for handling zero-cost and regular instructions. Only phis are handled separate now, since they should occurs first. Then, this patch adds checks to make use the MoveUse is set to the smallest value if there are multiple uses in a cycle. Patch by Brendon Cahoon. llvm-svn: 328540
30 lines
817 B
LLVM
30 lines
817 B
LLVM
; RUN: llc -march=hexagon -hexagon-bit=0 < %s
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; REQUIRES: asserts
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; Function Attrs: nounwind
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define void @f0() local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ 1, %b0 ], [ %v9, %b1 ]
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%v1 = phi i64 [ 0, %b0 ], [ %v10, %b1 ]
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%v2 = load i32, i32* undef, align 4
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%v3 = sub nsw i32 0, %v2
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%v4 = select i1 undef, i32 undef, i32 %v3
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%v5 = sext i32 %v4 to i64
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%v6 = mul nsw i64 %v5, %v5
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%v7 = or i64 %v1, 0
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%v8 = add i64 %v6, %v7
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%v9 = add nuw nsw i32 %v0, 1
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%v10 = and i64 %v8, -4294967296
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%v11 = icmp ult i32 %v9, undef
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br i1 %v11, label %b1, label %b2
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b2: ; preds = %b1
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%v12 = sdiv i64 %v8, undef
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv62" }
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