Jim Grosbach 0cd0534390 TableGen support for auto-generating assembly two-operand aliases. ... Assembly matchers for instructions with a two-operand form. ARM is full of these, for example: add {Rd}, Rn, Rm // Rd is optional and is the same as Rn if omitted. The property TwoOperandAliasConstraint on the instruction definition controls when, and if, an alias will be formed. No explicit InstAlias definitions are required. rdar://11255754 llvm-svn: 155172		2012-04-19 23:59:23 +00:00
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llvm	TableGen support for auto-generating assembly two-operand aliases.	2012-04-19 23:59:23 +00:00
llvm-c	Remove lto_codegen_set_whole_program_optimization. It is a work in progress,	2012-04-16 10:58:38 +00:00