mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
dd18739c8d
Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948
52 lines
1.1 KiB
LLVM
52 lines
1.1 KiB
LLVM
; RUN: llc < %s | FileCheck %s
|
|
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8:16"
|
|
target triple = "msp430-elf"
|
|
|
|
define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
|
|
entry:
|
|
; CHECK-LABEL: lshr8:
|
|
; CHECK: rrc.b
|
|
%shr = lshr i8 %a, %cnt
|
|
ret i8 %shr
|
|
}
|
|
|
|
define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
|
|
entry:
|
|
; CHECK-LABEL: ashr8:
|
|
; CHECK: rra.b
|
|
%shr = ashr i8 %a, %cnt
|
|
ret i8 %shr
|
|
}
|
|
|
|
define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
|
|
entry:
|
|
; CHECK: shl8
|
|
; CHECK: add.b
|
|
%shl = shl i8 %a, %cnt
|
|
ret i8 %shl
|
|
}
|
|
|
|
define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
|
|
entry:
|
|
; CHECK-LABEL: lshr16:
|
|
; CHECK: rrc
|
|
%shr = lshr i16 %a, %cnt
|
|
ret i16 %shr
|
|
}
|
|
|
|
define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
|
|
entry:
|
|
; CHECK-LABEL: ashr16:
|
|
; CHECK: rra
|
|
%shr = ashr i16 %a, %cnt
|
|
ret i16 %shr
|
|
}
|
|
|
|
define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
|
|
entry:
|
|
; CHECK-LABEL: shl16:
|
|
; CHECK: add
|
|
%shl = shl i16 %a, %cnt
|
|
ret i16 %shl
|
|
}
|