Guillaume Chatelet 7253f0aaf2 [LLVM][Alignment] Introduce Alignment In MachineFrameInfo ... Summary: This is patch is part of a serie to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: jfb Subscribers: hiraditya, dexonsmith, llvm-commits, courbet Tags: #llvm Differential Revision: https://reviews.llvm.org/D65800 llvm-svn: 369531		2019-08-21 14:29:30 +00:00
..
AsmParser	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
Disassembler	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
MCTargetDesc	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
TargetInfo	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
BitTracker.cpp	Use MCRegister in MCRegisterInfo's interfaces	2019-08-02 20:23:00 +00:00
BitTracker.h
CMakeLists.txt
Hexagon.h
Hexagon.td
HexagonAsmPrinter.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonAsmPrinter.h	Include what you use in HexagonAsmPrinter.h	2019-06-03 11:41:18 +00:00
HexagonBitSimplify.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonBitTracker.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonBitTracker.h
HexagonBlockRanges.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
HexagonBlockRanges.h
HexagonBranchRelaxation.cpp
HexagonCallingConv.td
HexagonCFGOptimizer.cpp
HexagonCommonGEP.cpp	[Hexagon] Remove indeterministic traversal order	2019-04-16 16:05:07 +00:00
HexagonConstExtenders.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonConstPropagation.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonCopyToCombine.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonDepArch.h
HexagonDepArch.td
HexagonDepDecoders.inc
HexagonDepIICHVX.td
HexagonDepIICScalar.td
HexagonDepInstrFormats.td
HexagonDepInstrInfo.td
HexagonDepITypes.h
HexagonDepITypes.td
HexagonDepMapAsm2Intrin.td
HexagonDepMappings.td
HexagonDepOperands.td
HexagonDepTimingClasses.h
HexagonEarlyIfConv.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonExpandCondsets.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonFixupHwLoops.cpp
HexagonFrameLowering.cpp	[LLVM][Alignment] Introduce Alignment In MachineFrameInfo	2019-08-21 14:29:30 +00:00
HexagonFrameLowering.h
HexagonGenExtract.cpp
HexagonGenInsert.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonGenMux.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonGenPredicate.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonHardwareLoops.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonHazardRecognizer.cpp
HexagonHazardRecognizer.h
HexagonIICHVX.td	[Hexagon] Avoid creating 5-instruction packets with vgather pseudos	2019-03-06 17:43:50 +00:00
HexagonIICScalar.td
HexagonInstrFormats.td
HexagonInstrFormatsV5.td
HexagonInstrFormatsV60.td
HexagonInstrFormatsV65.td
HexagonInstrInfo.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonInstrInfo.h	[PowerPC] Enable MachinePipeliner for P9 with -ppc-enable-pipeliner	2019-06-11 17:40:39 +00:00
HexagonIntrinsics.td
HexagonIntrinsicsV5.td
HexagonIntrinsicsV60.td
HexagonISelDAGToDAG.cpp
HexagonISelDAGToDAG.h
HexagonISelDAGToDAGHVX.cpp
HexagonISelLowering.cpp	[Hexagon] Generate min/max instructions for 64-bit vectors	2019-08-16 16:16:27 +00:00
HexagonISelLowering.h	[Hexagon] Generate min/max instructions for 64-bit vectors	2019-08-16 16:16:27 +00:00
HexagonISelLoweringHVX.cpp	[Hexagon] Generate vector min/max for HVX	2019-08-15 16:13:17 +00:00
HexagonLoopIdiomRecognition.cpp
HexagonMachineFunctionInfo.cpp
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp
HexagonMachineScheduler.h
HexagonMapAsm2IntrinV62.gen.td
HexagonMapAsm2IntrinV65.gen.td
HexagonMCInstLower.cpp
HexagonNewValueJump.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonOperands.td
HexagonOptAddrMode.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonOptimizeSZextends.cpp
HexagonPatterns.td	[Hexagon] Generate min/max instructions for 64-bit vectors	2019-08-16 16:16:27 +00:00
HexagonPatternsHVX.td	[Hexagon] Generate min/max instructions for 64-bit vectors	2019-08-16 16:16:27 +00:00
HexagonPatternsV65.td
HexagonPeephole.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonPseudo.td	[Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trap	2019-02-21 19:42:39 +00:00
HexagonRDFOpt.cpp
HexagonRegisterInfo.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonRegisterInfo.h	CodeGen: Introduce a class for registers	2019-06-24 15:50:29 +00:00
HexagonRegisterInfo.td
HexagonSchedule.td
HexagonScheduleV5.td
HexagonScheduleV55.td
HexagonScheduleV60.td
HexagonScheduleV62.td
HexagonScheduleV65.td
HexagonScheduleV66.td
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitConst32AndConst64.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonSplitDouble.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonStoreWidening.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonSubtarget.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonSubtarget.h
HexagonTargetMachine.cpp	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp	OpaquePtr: switch to GlobalValue::getValueType in a few places. NFC.	2019-07-11 13:13:02 +00:00
HexagonTargetObjectFile.h
HexagonTargetStreamer.h
HexagonTargetTransformInfo.cpp	[Hexagon] assert getRegisterBitWidth returns non-zero value. NFCI.	2019-05-22 12:25:46 +00:00
HexagonTargetTransformInfo.h	Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces"	2019-07-10 18:25:58 +00:00
HexagonVectorLoopCarriedReuse.cpp	[Hexagon] Rework VLCR algorithm	2019-07-01 13:50:47 +00:00
HexagonVectorPrint.cpp
HexagonVExtract.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonVLIWPacketizer.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonVLIWPacketizer.h
LLVMBuild.txt
RDFCopy.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
RDFCopy.h
RDFDeadCode.cpp
RDFDeadCode.h
RDFGraph.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
RDFGraph.h	Hexagon RDF: Replace function template (plus explicit specializations) with non-template overloads	2019-03-11 23:10:33 +00:00
RDFLiveness.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
RDFLiveness.h	Hexagon RDF: Replace function template (plus explicit specializations) with non-template overloads	2019-03-11 23:10:33 +00:00
RDFRegisters.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
RDFRegisters.h	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00