Craig Topper dd43e37f21 [AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX encoded VPXORD so all 32 registers can be used. ... llvm-svn: 268884		2016-05-08 21:33:53 +00:00
..
AArch64	[AArch64] Fix test to specify triple and disable post-RA scheduling.	2016-05-06 17:12:38 +00:00
AMDGPU	DetectDeadLanes: Increase precision when detecting undef inputs	2016-05-06 22:43:50 +00:00
ARM	[ARM] Fix Scavenger assert due to underestimated stack size	2016-05-08 05:11:54 +00:00
BPF
Generic
Hexagon	[Hexagon] Optimize addressing modes for load/store	2016-04-29 15:49:13 +00:00
Inputs
Lanai
Mips	[mips][mips16] Use isUnconditionalBranch() in AnalyzeBranch() and constant island pass.	2016-05-06 13:23:51 +00:00
MIR	ARM: fix handling of SUB immediates in peephole opt.	2016-05-02 18:30:08 +00:00
MSP430
NVPTX	[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection	2016-05-02 18:12:02 +00:00
PowerPC	[PowerPC] Generate VSX version of splat word	2016-05-04 16:04:02 +00:00
SPARC	[Sparc] Allow taking of function address into a register.	2016-05-04 12:11:05 +00:00
SystemZ	[SystemZ] Implement backchain attribute (recommit with fix).	2016-05-05 00:37:30 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Don't emit epilogue code in the middle of stackified code.	2016-05-05 20:41:15 +00:00
WinEH
X86	[AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX encoded VPXORD so all 32 registers can be used.	2016-05-08 21:33:53 +00:00
XCore