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ed11cfd166
Summary: See https://llvm.org/PR33743 for more details It seems that for non-power of 2 vector sizes, the algorithm can produce non-matching sizes for input and result causing an assert. This usually isn't a problem as the isAnyExtend check will weed these out, but in some cases (most often with lots of undefined values for the mask indices) it can pass this check for non power of 2 vectors. Adding in an extra check that ensures that bit size will match for the result and input (as required) Subscribers: nhaehnle Differential Revision: https://reviews.llvm.org/D35241 llvm-svn: 315307
33 lines
1.3 KiB
LLVM
33 lines
1.3 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; We are only checking that instruction selection can succeed in this case. This
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; cut down test results in no instructions, but that's fine.
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;
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; See https://llvm.org/PR33743 for details of the bug being addressed
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;
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; Checking that shufflevector with 3-vec mask is handled in
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; combineShuffleToVectorExtend
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;
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; GCN: s_endpgm
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define amdgpu_ps void @main(i32 %in1) local_unnamed_addr {
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.entry:
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br i1 undef, label %bb12, label %bb
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bb:
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%__llpc_global_proxy_r5.12.vec.insert = insertelement <4 x i32> undef, i32 %in1, i32 3
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%tmp3 = shufflevector <4 x i32> %__llpc_global_proxy_r5.12.vec.insert, <4 x i32> undef, <3 x i32> <i32 undef, i32 undef, i32 1>
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%tmp4 = bitcast <3 x i32> %tmp3 to <3 x float>
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%a2.i123 = extractelement <3 x float> %tmp4, i32 2
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%tmp5 = bitcast float %a2.i123 to i32
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%__llpc_global_proxy_r2.0.vec.insert196 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
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br label %bb12
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bb12:
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%__llpc_global_proxy_r2.0 = phi <4 x i32> [ %__llpc_global_proxy_r2.0.vec.insert196, %bb ], [ undef, %.entry ]
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%tmp6 = shufflevector <4 x i32> %__llpc_global_proxy_r2.0, <4 x i32> undef, <3 x i32> <i32 1, i32 2, i32 3>
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%tmp7 = bitcast <3 x i32> %tmp6 to <3 x float>
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%a0.i = extractelement <3 x float> %tmp7, i32 0
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ret void
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}
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