mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 13:02:52 +02:00
67fea7a094
Summary: I checked the AMD closed source compiler and the workaround is only needed when x3 is emulated as x4, which we don't do in LLVM. SMEM x3 opcodes don't exist, and instead there is a possibility to use x4 with the last component being unused. If the last component is out of buffer bounds and falls on the next 4K page, the hw hangs. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D42756 llvm-svn: 324486
297 lines
15 KiB
LLVM
297 lines
15 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SICI -check-prefix=SIVIGFX9 %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=SICI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s
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; SMRD load with an immediate offset.
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; GCN-LABEL: {{^}}smrd0:
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
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; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
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define amdgpu_kernel void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 {
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entry:
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%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 1
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%tmp1 = load i32, i32 addrspace(2)* %tmp
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with the largest possible immediate offset.
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; GCN-LABEL: {{^}}smrd1:
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
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; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
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define amdgpu_kernel void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 {
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entry:
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%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 255
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%tmp1 = load i32, i32 addrspace(2)* %tmp
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate.
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; GCN-LABEL: {{^}}smrd2:
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; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
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; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
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; GCN: s_endpgm
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define amdgpu_kernel void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 {
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entry:
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%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 256
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%tmp1 = load i32, i32 addrspace(2)* %tmp
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with a 64-bit offset
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; GCN-LABEL: {{^}}smrd3:
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; FIXME: There are too many copies here because we don't fold immediates
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; through REG_SEQUENCE
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; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
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; TODO: Add VI checks
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; GCN: s_endpgm
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define amdgpu_kernel void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 {
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entry:
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%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 4294967296
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%tmp1 = load i32, i32 addrspace(2)* %tmp
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with the largest possible immediate offset on VI
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; GCN-LABEL: {{^}}smrd4:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
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; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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define amdgpu_kernel void @smrd4(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 {
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entry:
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%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 262143
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%tmp1 = load i32, i32 addrspace(2)* %tmp
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd5:
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; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SIVIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
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; GCN: s_endpgm
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define amdgpu_kernel void @smrd5(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 {
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entry:
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%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 262144
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%tmp1 = load i32, i32 addrspace(2)* %tmp
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}smrd_hazard:
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; GCN-DAG: s_mov_b32 s3, 3
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; GCN-DAG: s_mov_b32 s2, 2
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; GCN-DAG: s_mov_b32 s1, 1
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; GCN-DAG: s_mov_b32 s0, 0
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; SI-NEXT: nop 3
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; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x0
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define amdgpu_ps float @smrd_hazard(<4 x i32> inreg %desc) #0 {
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main_body:
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%d0 = insertelement <4 x i32> undef, i32 0, i32 0
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%d1 = insertelement <4 x i32> %d0, i32 1, i32 1
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%d2 = insertelement <4 x i32> %d1, i32 2, i32 2
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%d3 = insertelement <4 x i32> %d2, i32 3, i32 3
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%r = call float @llvm.SI.load.const.v4i32(<4 x i32> %d3, i32 0)
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ret float %r
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}
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; SMRD load using the load.const.v4i32 intrinsic with an immediate offset
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; GCN-LABEL: {{^}}smrd_load_const0:
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; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
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; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10
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define amdgpu_ps void @smrd_load_const0(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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main_body:
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%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp
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%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
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ret void
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}
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; SMRD load using the load.const.v4i32 intrinsic with the largest possible immediate
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; offset.
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; GCN-LABEL: {{^}}smrd_load_const1:
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; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
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; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
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define amdgpu_ps void @smrd_load_const1(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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main_body:
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%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp
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%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1020)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
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ret void
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}
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; SMRD load using the load.const.v4i32 intrinsic with an offset greater than the
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; largets possible immediate.
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; immediate offset.
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; GCN-LABEL: {{^}}smrd_load_const2:
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; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
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; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
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define amdgpu_ps void @smrd_load_const2(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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main_body:
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%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp
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%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1024)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
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ret void
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}
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; SMRD load with the largest possible immediate offset on VI
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; GCN-LABEL: {{^}}smrd_load_const3:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
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; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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define amdgpu_ps void @smrd_load_const3(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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main_body:
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%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp
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%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1048572)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd_load_const4:
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; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SIVIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
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; GCN: s_endpgm
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define amdgpu_ps void @smrd_load_const4(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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main_body:
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%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp
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%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1048576)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
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ret void
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}
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; GCN-LABEL: {{^}}smrd_sgpr_offset:
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; GCN: s_buffer_load_dword s{{[0-9]}}, s[0:3], s4
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define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 {
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main_body:
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%r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset)
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ret float %r
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}
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; GCN-LABEL: {{^}}smrd_vgpr_offset:
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; GCN: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ;
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define amdgpu_ps float @smrd_vgpr_offset(<4 x i32> inreg %desc, i32 %offset) #0 {
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main_body:
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%r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset)
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ret float %r
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}
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; GCN-LABEL: {{^}}smrd_vgpr_offset_imm:
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; GCN-NEXT: %bb.
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; GCN-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen offset:4095 ;
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define amdgpu_ps float @smrd_vgpr_offset_imm(<4 x i32> inreg %desc, i32 %offset) #0 {
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main_body:
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%off = add i32 %offset, 4095
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%r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %off)
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ret float %r
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}
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; GCN-LABEL: {{^}}smrd_vgpr_offset_imm_too_large:
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; GCN-NEXT: %bb.
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; GCN-NEXT: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}0x1000, v0
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; GCN-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ;
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define amdgpu_ps float @smrd_vgpr_offset_imm_too_large(<4 x i32> inreg %desc, i32 %offset) #0 {
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main_body:
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%off = add i32 %offset, 4096
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%r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %off)
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ret float %r
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}
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; GCN-LABEL: {{^}}smrd_imm_merged:
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; GCN-NEXT: %bb.
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; SICI-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1
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; SICI-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x7
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; VIGFX9-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x4
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; VIGFX9-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1c
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define amdgpu_ps void @smrd_imm_merged(<4 x i32> inreg %desc) #0 {
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main_body:
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%r1 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 4)
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%r2 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 8)
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%r3 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 12)
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%r4 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 16)
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%r5 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 28)
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%r6 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 32)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0
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ret void
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}
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; GCN-LABEL: {{^}}smrd_vgpr_merged:
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; GCN-NEXT: %bb.
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; GCN-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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; GCN-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
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define amdgpu_ps void @smrd_vgpr_merged(<4 x i32> inreg %desc, i32 %a) #0 {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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%a4 = add i32 %a, 16
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%a5 = add i32 %a, 28
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%a6 = add i32 %a, 32
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%r1 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a1)
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%r2 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a2)
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%r3 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a3)
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%r4 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a4)
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%r5 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a5)
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%r6 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a6)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0
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ret void
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}
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; GCN-LABEL: {{^}}smrd_sgpr_descriptor_promoted
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; GCN: v_readfirstlane
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define amdgpu_cs void @smrd_sgpr_descriptor_promoted([0 x i8] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), i32) #0 {
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main_body:
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%descptr = bitcast [0 x i8] addrspace(2)* %0 to <4 x i32> addrspace(2)*, !amdgpu.uniform !0
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br label %.outer_loop_header
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|
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ret_block: ; preds = %.outer, %.label22, %main_body
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|
ret void
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|
|
|
.outer_loop_header:
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|
br label %.inner_loop_header
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|
|
|
.inner_loop_header: ; preds = %.inner_loop_body, %.outer_loop_header
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|
%loopctr.1 = phi i32 [ 0, %.outer_loop_header ], [ %loopctr.2, %.inner_loop_body ]
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|
%loopctr.2 = add i32 %loopctr.1, 1
|
|
%inner_br1 = icmp slt i32 %loopctr.2, 10
|
|
br i1 %inner_br1, label %.inner_loop_body, label %ret_block
|
|
|
|
.inner_loop_body:
|
|
%descriptor = load <4 x i32>, <4 x i32> addrspace(2)* %descptr, align 16, !invariant.load !0
|
|
%load1result = call float @llvm.SI.load.const.v4i32(<4 x i32> %descriptor, i32 0)
|
|
%inner_br2 = icmp uge i32 %1, 10
|
|
br i1 %inner_br2, label %.inner_loop_header, label %.outer_loop_body
|
|
|
|
.outer_loop_body:
|
|
%offset = shl i32 %loopctr.2, 6
|
|
%load2result = call float @llvm.SI.load.const.v4i32(<4 x i32> %descriptor, i32 %offset)
|
|
%outer_br = fcmp ueq float %load2result, 0x0
|
|
br i1 %outer_br, label %.outer_loop_header, label %ret_block
|
|
}
|
|
|
|
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
|
declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|
|
|
|
!0 = !{}
|