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278 lines
9.5 KiB
TableGen
278 lines
9.5 KiB
TableGen
//===- BlackfinRegisterInfo.td - Blackfin Register defs ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the Blackfin register file
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//===----------------------------------------------------------------------===//
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// Subregs are:
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// 1: .L
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// 2: .H
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// 3: .W (32 low bits of 40-bit accu)
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let Namespace = "BF" in {
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def lo16 : SubRegIndex;
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def hi16 : SubRegIndex;
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def lo32 : SubRegIndex;
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def hi32 : SubRegIndex;
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}
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// Registers are identified with 3-bit group and 3-bit ID numbers.
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class BlackfinReg<string n> : Register<n> {
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field bits<3> Group;
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field bits<3> Num;
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let Namespace = "BF";
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}
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// Rc - 1-bit registers
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class Rc<bits<5> bitno, string n> : BlackfinReg<n> {
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field bits<5> BitNum = bitno;
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}
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// Rs - 16-bit integer registers
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class Rs<bits<3> group, bits<3> num, bits<1> hi, string n> : BlackfinReg<n> {
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let Group = group;
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let Num = num;
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field bits<1> High = hi;
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}
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// Ri - 32-bit integer registers with subregs
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class Ri<bits<3> group, bits<3> num, string n> : BlackfinReg<n> {
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let Group = group;
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let Num = num;
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}
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// Ra 40-bit accumulator registers
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class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> {
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let SubRegs = subs;
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let SubRegIndices = [hi32, lo32];
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let Group = 4;
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let Num = num;
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}
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// Two halves of 32-bit register
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multiclass Rss<bits<3> group, bits<3> num, string n> {
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def H : Rs<group, num, 1, !strconcat(n, ".h")>;
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def L : Rs<group, num, 0, !strconcat(n, ".l")>;
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}
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// Rii - 32-bit integer registers with subregs
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class Rii<bits<3> group, bits<3> num, string n, list<Register> subs>
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: BlackfinReg<n> {
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let SubRegs = subs;
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let SubRegIndices = [hi16, lo16];
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let Group = group;
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let Num = num;
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}
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// Status bits are all part of ASTAT
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def AZ : Rc<0, "az">;
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def AN : Rc<1, "an">;
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def CC : Rc<5, "cc">, DwarfRegNum<[34]>;
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def NCC : Rc<5, "!cc"> { let Aliases = [CC]; }
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def AQ : Rc<6, "aq">;
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def AC0 : Rc<12, "ac0">;
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def AC1 : Rc<13, "ac1">;
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def AV0 : Rc<16, "av0">;
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def AV0S : Rc<17, "av0s">;
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def AV1 : Rc<18, "av1">;
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def AV1S : Rc<19, "av1s">;
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def V : Rc<24, "v">;
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def VS : Rc<25, "vs">;
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// Skipped non-status bits: AC0_COPY, V_COPY, RND_MOD
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// Group 0: Integer registers
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defm R0 : Rss<0, 0, "r0">;
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def R0 : Rii<0, 0, "r0", [R0H, R0L]>, DwarfRegNum<[0]>;
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defm R1 : Rss<0, 1, "r1">;
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def R1 : Rii<0, 1, "r1", [R1H, R1L]>, DwarfRegNum<[1]>;
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defm R2 : Rss<0, 2, "r2">;
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def R2 : Rii<0, 2, "r2", [R2H, R2L]>, DwarfRegNum<[2]>;
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defm R3 : Rss<0, 3, "r3">;
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def R3 : Rii<0, 3, "r3", [R3H, R3L]>, DwarfRegNum<[3]>;
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defm R4 : Rss<0, 4, "r4">;
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def R4 : Rii<0, 4, "r4", [R4H, R4L]>, DwarfRegNum<[4]>;
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defm R5 : Rss<0, 5, "r5">;
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def R5 : Rii<0, 5, "r5", [R5H, R5L]>, DwarfRegNum<[5]>;
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defm R6 : Rss<0, 6, "r6">;
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def R6 : Rii<0, 6, "r6", [R6H, R6L]>, DwarfRegNum<[6]>;
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defm R7 : Rss<0, 7, "r7">;
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def R7 : Rii<0, 7, "r7", [R7H, R7L]>, DwarfRegNum<[7]>;
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// Group 1: Pointer registers
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defm P0 : Rss<1, 0, "p0">;
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def P0 : Rii<1, 0, "p0", [P0H, P0L]>, DwarfRegNum<[8]>;
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defm P1 : Rss<1, 1, "p1">;
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def P1 : Rii<1, 1, "p1", [P1H, P1L]>, DwarfRegNum<[9]>;
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defm P2 : Rss<1, 2, "p2">;
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def P2 : Rii<1, 2, "p2", [P2H, P2L]>, DwarfRegNum<[10]>;
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defm P3 : Rss<1, 3, "p3">;
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def P3 : Rii<1, 3, "p3", [P3H, P3L]>, DwarfRegNum<[11]>;
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defm P4 : Rss<1, 4, "p4">;
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def P4 : Rii<1, 4, "p4", [P4H, P4L]>, DwarfRegNum<[12]>;
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defm P5 : Rss<1, 5, "p5">;
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def P5 : Rii<1, 5, "p5", [P5H, P5L]>, DwarfRegNum<[13]>;
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defm SP : Rss<1, 6, "sp">;
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def SP : Rii<1, 6, "sp", [SPH, SPL]>, DwarfRegNum<[14]>;
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defm FP : Rss<1, 7, "fp">;
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def FP : Rii<1, 7, "fp", [FPH, FPL]>, DwarfRegNum<[15]>;
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// Group 2: Index registers
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defm I0 : Rss<2, 0, "i0">;
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def I0 : Rii<2, 0, "i0", [I0H, I0L]>, DwarfRegNum<[16]>;
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defm I1 : Rss<2, 1, "i1">;
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def I1 : Rii<2, 1, "i1", [I1H, I1L]>, DwarfRegNum<[17]>;
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defm I2 : Rss<2, 2, "i2">;
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def I2 : Rii<2, 2, "i2", [I2H, I2L]>, DwarfRegNum<[18]>;
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defm I3 : Rss<2, 3, "i3">;
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def I3 : Rii<2, 3, "i3", [I3H, I3L]>, DwarfRegNum<[19]>;
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defm M0 : Rss<2, 4, "m0">;
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def M0 : Rii<2, 4, "m0", [M0H, M0L]>, DwarfRegNum<[20]>;
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defm M1 : Rss<2, 5, "m1">;
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def M1 : Rii<2, 5, "m1", [M1H, M1L]>, DwarfRegNum<[21]>;
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defm M2 : Rss<2, 6, "m2">;
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def M2 : Rii<2, 6, "m2", [M2H, M2L]>, DwarfRegNum<[22]>;
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defm M3 : Rss<2, 7, "m3">;
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def M3 : Rii<2, 7, "m3", [M3H, M3L]>, DwarfRegNum<[23]>;
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// Group 3: Cyclic indexing registers
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defm B0 : Rss<3, 0, "b0">;
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def B0 : Rii<3, 0, "b0", [B0H, B0L]>, DwarfRegNum<[24]>;
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defm B1 : Rss<3, 1, "b1">;
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def B1 : Rii<3, 1, "b1", [B1H, B1L]>, DwarfRegNum<[25]>;
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defm B2 : Rss<3, 2, "b2">;
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def B2 : Rii<3, 2, "b2", [B2H, B2L]>, DwarfRegNum<[26]>;
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defm B3 : Rss<3, 3, "b3">;
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def B3 : Rii<3, 3, "b3", [B3H, B3L]>, DwarfRegNum<[27]>;
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defm L0 : Rss<3, 4, "l0">;
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def L0 : Rii<3, 4, "l0", [L0H, L0L]>, DwarfRegNum<[28]>;
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defm L1 : Rss<3, 5, "l1">;
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def L1 : Rii<3, 5, "l1", [L1H, L1L]>, DwarfRegNum<[29]>;
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defm L2 : Rss<3, 6, "l2">;
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def L2 : Rii<3, 6, "l2", [L2H, L2L]>, DwarfRegNum<[30]>;
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defm L3 : Rss<3, 7, "l3">;
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def L3 : Rii<3, 7, "l3", [L3H, L3L]>, DwarfRegNum<[31]>;
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// Accumulators
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def A0X : Ri <4, 0, "a0.x">;
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defm A0 : Rss<4, 1, "a0">;
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def A0W : Rii<4, 1, "a0.w", [A0H, A0L]>, DwarfRegNum<[32]>;
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def A0 : Ra <0, "a0", [A0X, A0W]>;
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def A1X : Ri <4, 2, "a1.x">;
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defm A1 : Rss<4, 3, "a1">;
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def A1W : Rii<4, 3, "a1.w", [A1H, A1L]>, DwarfRegNum<[33]>;
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def A1 : Ra <2, "a1", [A1X, A1W]>;
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def RETS : Ri<4, 7, "rets">, DwarfRegNum<[35]>;
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def RETI : Ri<7, 3, "reti">, DwarfRegNum<[36]>;
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def RETX : Ri<7, 4, "retx">, DwarfRegNum<[37]>;
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def RETN : Ri<7, 5, "retn">, DwarfRegNum<[38]>;
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def RETE : Ri<7, 6, "rete">, DwarfRegNum<[39]>;
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def ASTAT : Ri<4, 6, "astat">, DwarfRegNum<[40]> {
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let Aliases = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS];
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}
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def SEQSTAT : Ri<7, 1, "seqstat">, DwarfRegNum<[41]>;
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def USP : Ri<7, 0, "usp">, DwarfRegNum<[42]>;
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def EMUDAT : Ri<7, 7, "emudat">, DwarfRegNum<[43]>;
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def SYSCFG : Ri<7, 2, "syscfg">;
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def CYCLES : Ri<6, 6, "cycles">;
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def CYCLES2 : Ri<6, 7, "cycles2">;
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// Hardware loops
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def LT0 : Ri<6, 1, "lt0">, DwarfRegNum<[44]>;
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def LT1 : Ri<6, 4, "lt1">, DwarfRegNum<[45]>;
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def LC0 : Ri<6, 0, "lc0">, DwarfRegNum<[46]>;
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def LC1 : Ri<6, 3, "lc1">, DwarfRegNum<[47]>;
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def LB0 : Ri<6, 2, "lb0">, DwarfRegNum<[48]>;
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def LB1 : Ri<6, 5, "lb1">, DwarfRegNum<[49]>;
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// Register classes.
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def D16L : RegisterClass<"BF", [i16], 16, (sequence "R%uL", 0, 7)>;
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def D16H : RegisterClass<"BF", [i16], 16, (sequence "R%uH", 0, 7)>;
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def D16 : RegisterClass<"BF", [i16], 16, (add D16L, D16H)>;
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def P16L : RegisterClass<"BF", [i16], 16,
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(add (sequence "P%uL", 0, 5), SPL, FPL)>;
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def P16H : RegisterClass<"BF", [i16], 16,
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(add (sequence "P%uH", 0, 5), SPH, FPH)>;
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def P16 : RegisterClass<"BF", [i16], 16, (add P16L, P16H)>;
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def DP16 : RegisterClass<"BF", [i16], 16, (add D16, P16)>;
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def DP16L : RegisterClass<"BF", [i16], 16, (add D16L, P16L)>;
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def DP16H : RegisterClass<"BF", [i16], 16, (add D16H, P16H)>;
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def GR16 : RegisterClass<"BF", [i16], 16,
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(add DP16,
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I0H, I0L, I1H, I1L, I2H, I2L, I3H, I3L,
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M0H, M0L, M1H, M1L, M2H, M2L, M3H, M3L,
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B0H, B0L, B1H, B1L, B2H, B2L, B3H, B3L,
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L0H, L0L, L1H, L1L, L2H, L2L, L3H, L3L)>;
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def D : RegisterClass<"BF", [i32], 32, (sequence "R%u", 0, 7)> {
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let SubRegClasses = [(D16L lo16), (D16H hi16)];
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}
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def P : RegisterClass<"BF", [i32], 32, (add (sequence "P%u", 0, 5), FP, SP)> {
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let SubRegClasses = [(P16L lo16), (P16H hi16)];
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}
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def DP : RegisterClass<"BF", [i32], 32, (add D, P)> {
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let SubRegClasses = [(DP16L lo16), (DP16H hi16)];
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}
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def I : RegisterClass<"BF", [i32], 32, (add I0, I1, I2, I3)>;
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def M : RegisterClass<"BF", [i32], 32, (add M0, M1, M2, M3)>;
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def B : RegisterClass<"BF", [i32], 32, (add B0, B1, B2, B3)>;
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def L : RegisterClass<"BF", [i32], 32, (add L0, L1, L2, L3)>;
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def GR : RegisterClass<"BF", [i32], 32, (add DP, I, M, B, L)>;
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def ALL : RegisterClass<"BF", [i32], 32,
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(add GR,
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A0X, A0W, A1X, A1W, ASTAT, RETS,
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LC0, LT0, LB0, LC1, LT1, LB1, CYCLES, CYCLES2,
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USP, SEQSTAT, SYSCFG, RETI, RETX, RETN, RETE, EMUDAT)>;
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def PI : RegisterClass<"BF", [i32], 32, (add P, I)>;
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// We are going to pretend that CC and !CC are 32-bit registers, even though
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// they only can hold 1 bit.
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let CopyCost = -1, Size = 8 in {
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def JustCC : RegisterClass<"BF", [i32], 8, (add CC)>;
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def NotCC : RegisterClass<"BF", [i32], 8, (add NCC)>;
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def AnyCC : RegisterClass<"BF", [i32], 8, (add CC, NCC)>;
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def StatBit : RegisterClass<"BF", [i1], 8,
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(add AZ, AN, CC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS)>;
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}
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// Should be i40, but that isn't defined. It is not a legal type yet anyway.
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def Accu : RegisterClass<"BF", [i64], 64, (add A0, A1)>;
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// Register classes to match inline asm constraints.
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def zCons : RegisterClass<"BF", [i32], 32, (add P0, P1, P2)>;
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def DCons : RegisterClass<"BF", [i32], 32, (add R0, R2, R4, R6)>;
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def WCons : RegisterClass<"BF", [i32], 32, (add R1, R3, R5, R7)>;
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def cCons : RegisterClass<"BF", [i32], 32, (add I0, I1, I2, I3,
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B0, B1, B2, B3,
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L0, L1, L2, L3)>;
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def tCons : RegisterClass<"BF", [i32], 32, (add LT0, LT1)>;
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def uCons : RegisterClass<"BF", [i32], 32, (add LB0, LB1)>;
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def kCons : RegisterClass<"BF", [i32], 32, (add LC0, LC1)>;
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def yCons : RegisterClass<"BF", [i32], 32, (add RETS, RETN, RETI, RETX,
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RETE, ASTAT, SEQSTAT,
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USP)>;
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