mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
58 lines
1.4 KiB
LLVM
58 lines
1.4 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
|
|
|
|
target triple = "hexagon"
|
|
|
|
; CHECK-LABEL: xh_sh
|
|
; CHECK: sath
|
|
; CHECK-NOT: sxth
|
|
define i32 @xh_sh(i32 %x) local_unnamed_addr #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.A2.sath(i32 %x)
|
|
%1 = tail call i32 @llvm.hexagon.A2.sxth(i32 %0)
|
|
ret i32 %1
|
|
}
|
|
|
|
; CHECK-LABEL: xb_sb
|
|
; CHECK: satb
|
|
; CHECK-NOT: sxtb
|
|
define i32 @xb_sb(i32 %x) local_unnamed_addr #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.A2.satb(i32 %x)
|
|
%1 = tail call i32 @llvm.hexagon.A2.sxtb(i32 %0)
|
|
ret i32 %1
|
|
}
|
|
|
|
; CHECK-LABEL: xuh_suh
|
|
; CHECK: satuh
|
|
; CHECK-NOT: zxth
|
|
define i32 @xuh_suh(i32 %x) local_unnamed_addr #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.A2.satuh(i32 %x)
|
|
%1 = tail call i32 @llvm.hexagon.A2.zxth(i32 %0)
|
|
ret i32 %1
|
|
}
|
|
|
|
; CHECK-LABEL: xub_sub
|
|
; CHECK: satub
|
|
; CHECK-NOT: zxtb
|
|
define i32 @xub_sub(i32 %x) local_unnamed_addr #0 {
|
|
entry:
|
|
%0 = tail call i32 @llvm.hexagon.A2.satub(i32 %x)
|
|
%1 = tail call i32 @llvm.hexagon.A2.zxtb(i32 %0)
|
|
ret i32 %1
|
|
}
|
|
|
|
|
|
declare i32 @llvm.hexagon.A2.sxtb(i32) #1
|
|
declare i32 @llvm.hexagon.A2.sxth(i32) #1
|
|
declare i32 @llvm.hexagon.A2.zxtb(i32) #1
|
|
declare i32 @llvm.hexagon.A2.zxth(i32) #1
|
|
|
|
declare i32 @llvm.hexagon.A2.satb(i32) #1
|
|
declare i32 @llvm.hexagon.A2.sath(i32) #1
|
|
declare i32 @llvm.hexagon.A2.satub(i32) #1
|
|
declare i32 @llvm.hexagon.A2.satuh(i32) #1
|
|
|
|
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
|
|
attributes #1 = { nounwind readnone }
|