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llvm-mirror/test/CodeGen/Hexagon/isel-select-v4i8.ll
Krzysztof Parzyszek 886e13050e [Hexagon] Don't generate short vectors in ISD::SELECT in preprocessing
Selection DAG preprocessing runs long after legalization, so make sure
that the types can be handled by the selection code.
2020-02-11 15:27:33 -06:00

36 lines
1.4 KiB
LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; This used to fail:
; LLVM ERROR: Cannot select: t54: v4i8 = select t50, t53, t52
; CHECK: jumpr r31
target triple = "hexagon"
@g0 = external dso_local unnamed_addr constant [41 x i8], align 1
define dso_local void @f0() local_unnamed_addr #0 {
b0:
%v0 = load <16 x i32>, <16 x i32>* undef, align 16
%v1 = icmp eq <16 x i32> %v0, zeroinitializer
%v2 = or <16 x i1> %v1, zeroinitializer
%v3 = or <16 x i1> %v2, zeroinitializer
%v4 = or <16 x i1> %v3, zeroinitializer
%v5 = shufflevector <16 x i1> %v4, <16 x i1> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%v6 = or <16 x i1> %v4, %v5
%v7 = extractelement <16 x i1> %v6, i32 0
%v8 = or i1 %v7, undef
%v9 = or i1 %v8, undef
br i1 %v9, label %b2, label %b1
b1: ; preds = %b0
call void (i8*, ...) @f1(i8* getelementptr inbounds ([41 x i8], [41 x i8]* @g0, i32 0, i32 0))
unreachable
b2: ; preds = %b0
ret void
}
declare dso_local void @f1(i8*, ...) local_unnamed_addr #1
attributes #0 = { "target-cpu"="hexagonv66" "target-features"="+hvx-length64b,+hvxv66,+v66,-long-calls" }
attributes #1 = { "use-soft-float"="false" }