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45 lines
1.1 KiB
LLVM
45 lines
1.1 KiB
LLVM
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
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; Test that we do generate max #u5 in memops.
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; CHECK: memh(r{{[0-9]+}}+#0) -= #31
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@g0 = unnamed_addr global i16 -32, align 2
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; Function Attrs: norecurse nounwind
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define fastcc void @f0() unnamed_addr #0 {
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b0:
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%v0 = load i16, i16* @g0, align 1, !tbaa !4
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%v1 = zext i16 %v0 to i32
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%v2 = mul nuw nsw i32 %v1, 9625
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%v3 = and i32 %v2, 255
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%v4 = mul nuw nsw i32 %v3, 9625
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%v5 = and i32 %v4, 255
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%v6 = trunc i32 %v5 to i16
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store i16 %v6, i16* @g0, align 2, !tbaa !4
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ret void
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}
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define i32 @f1() {
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b0:
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%v0 = load i16, i16* @g0, align 2, !tbaa !4
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%v1 = zext i16 %v0 to i32
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%v2 = add nuw nsw i32 %v1, 65505
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%v3 = trunc i32 %v2 to i16
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store i16 %v3, i16* @g0, align 2, !tbaa !4
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tail call fastcc void @f0()
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%v4 = load i16, i16* @g0, align 2, !tbaa !4
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%v5 = zext i16 %v4 to i32
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ret i32 %v5
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv55" }
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!llvm.module.flags = !{!0, !2}
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!0 = !{i32 6, !"Target CPU", !1}
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!1 = !{!"hexagonv55"}
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!2 = !{i32 6, !"Target Features", !3}
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!3 = !{!"-hvx"}
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!4 = !{!5, !5, i64 0}
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!5 = !{!"omnipotent char", !6, i64 0}
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!6 = !{!"Simple C/C++ TBAA"}
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