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57fe353199
This is a part of https://reviews.llvm.org/D47735. llvm-svn: 356683
91 lines
2.3 KiB
LLVM
91 lines
2.3 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; OR of two rotates of %a0(r0).
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; CHECK-LABEL: f0:
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; CHECK: r[[R00:[0-9]+]] = rol(r0,#7)
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; CHECK: r[[R00]] |= rol(r0,#9)
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define i32 @f0(i32 %a0) #0 {
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b0:
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%v0 = shl i32 %a0, 7
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%v1 = lshr i32 %a0, 25
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%v2 = or i32 %v0, %v1
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%v3 = shl i32 %a0, 9
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%v4 = lshr i32 %a0, 23
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%v5 = or i32 %v3, %v4
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%v6 = or i32 %v2, %v5
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ret i32 %v6
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}
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; OR of two rotates of %a0(r0) with an extra input %a1(r1).
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; CHECK-LABEL: f1:
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; CHECK: r1 |= asl(r0,#7)
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; CHECK: r1 |= rol(r0,#9)
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define i32 @f1(i32 %a0, i32 %a1) #0 {
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b0:
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%v0 = shl i32 %a0, 7
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%v1 = lshr i32 %a0, 25
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%v2 = or i32 %v0, %a1
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%v3 = shl i32 %a0, 9
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%v4 = lshr i32 %a0, 23
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%v5 = or i32 %v3, %v4
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%v6 = or i32 %v2, %v5
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%v7 = or i32 %v6, %v1
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ret i32 %v6
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}
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; OR of two rotates of two different inputs: %a0(r0) and %a1(r1).
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; CHECK-LABEL: f2:
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; CHECK: r[[R20:[0-9]+]] = asl(r0,#11)
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; CHECK: r[[R21:[0-9]+]] = lsr(r0,#21)
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; CHECK: r[[R22:[0-9]+]] = lsr(r1,#13)
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; CHECK: r[[R20]] |= asl(r1,#19)
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; CHECK: r[[R20]] |= or(r[[R21]],r[[R22]])
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define i32 @f2(i32 %a0, i32 %a1) #0 {
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%v0 = shl i32 %a0, 11
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%v1 = lshr i32 %a0, 21
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%v2 = shl i32 %a1, 19
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%v3 = lshr i32 %a1, 13
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%v4 = or i32 %v0, %v2
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%v5 = or i32 %v1, %v3
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%v6 = or i32 %v4, %v5
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ret i32 %v6
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}
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; ORs of multiple shifts of the same value with only one pair actually
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; matching a rotate.
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; CHECK-LABEL: f3:
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; CHECK: r[[R30:[0-9]+]] = asl(r0,#3)
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; CHECK: r[[R30]] |= asl(r0,#5)
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; CHECK: r[[R30]] |= asl(r0,#7)
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; CHECK: r[[R30]] |= asl(r0,#13)
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; CHECK: r[[R30]] |= asl(r0,#19)
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; CHECK: r[[R30]] |= lsr(r0,#2)
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; CHECK: r[[R30]] |= lsr(r0,#15)
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; CHECK: r[[R30]] |= lsr(r0,#23)
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; CHECK: r[[R30]] |= lsr(r0,#25)
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; CHECK: r[[R30]] |= lsr(r0,#30)
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define i32 @f3(i32 %a0) #0 {
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%v0 = shl i32 %a0, 3
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%v1 = shl i32 %a0, 5
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%v2 = shl i32 %a0, 7 ; rotate
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%v3 = shl i32 %a0, 13
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%v4 = shl i32 %a0, 19
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%v5 = lshr i32 %a0, 2
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%v6 = lshr i32 %a0, 15
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%v7 = lshr i32 %a0, 23
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%v8 = lshr i32 %a0, 25 ; rotate
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%v9 = lshr i32 %a0, 30
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%v10 = or i32 %v0, %v1
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%v11 = or i32 %v10, %v2
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%v12 = or i32 %v11, %v3
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%v13 = or i32 %v12, %v4
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%v14 = or i32 %v13, %v5
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%v15 = or i32 %v14, %v6
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%v16 = or i32 %v15, %v7
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%v17 = or i32 %v16, %v8
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%v18 = or i32 %v17, %v9
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ret i32 %v18
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}
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attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="-packets" }
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