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25cc728d30
Summary: This extends the PeelingModuloScheduleExpander to generate prolog and epilog code, and correctly stitch uses through the prolog, kernel, epilog DAG. The key concept in this patch is to ensure that all transforms are *local*; only a function of a block and its immediate predecessor and successor. By defining the problem in this way we can inductively rewrite the entire DAG using only local knowledge that is easy to reason about. For example, we assume that all prologs and epilogs are near-perfect clones of the steady-state kernel. This means that if a block has an instruction that is predicated out, we can redirect all users of that instruction to that equivalent instruction in our immediate predecessor. As all blocks are clones, every instruction must have an equivalent in every other block. Similarly we can make the assumption by construction that if a value defined in a block is used outside that block, the only possible user is its immediate successors. We maintain this even for values that are used outside the loop by creating a limited form of LCSSA. This code isn't small, but it isn't complex. Enabled a bunch of testing from Hexagon. There are a couple of tests not enabled yet; I'm about 80% sure there isn't buggy codegen but the tests are checking for patterns that we don't produce. Those still need a bit more investigation. In the meantime we (Google) are happy with the code produced by this on our downstream SMS implementation, and believe it generates correct code. Subscribers: mgorny, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68205 llvm-svn: 373462
62 lines
2.0 KiB
LLVM
62 lines
2.0 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
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; Test that we generate the correct offsets for loads in the prolog
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; after removing dependences on a post-increment instructions of the
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; base register.
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; CHECK: memh([[REG0:(r[0-9]+)]]+#0)
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; CHECK: memh([[REG0]]+#2)
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; CHECK: loop0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.sath(i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.asrh(i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.addsat(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) #1
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define void @f0(i32 %a0) #0 align 2 {
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b0:
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br label %b1
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b1: ; preds = %b0
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br label %b2
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b2: ; preds = %b2, %b1
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%v0 = phi i16* [ undef, %b1 ], [ %v14, %b2 ]
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%v1 = phi i32 [ 0, %b1 ], [ %v12, %b2 ]
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%v2 = load i16, i16* %v0, align 2
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%v3 = sext i16 %v2 to i32
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%v4 = call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 undef, i32 %v3)
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%v5 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v4, i32 undef)
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%v6 = call i32 @llvm.hexagon.A2.addsat(i32 %v5, i32 32768)
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%v7 = call i32 @llvm.hexagon.A2.asrh(i32 %v6)
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%v8 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v7, i32 undef)
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%v9 = call i32 @llvm.hexagon.A2.sath(i32 %v8)
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%v10 = trunc i32 %v9 to i16
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store i16 %v10, i16* null, align 2
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%v11 = trunc i32 %v7 to i16
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store i16 %v11, i16* %v0, align 2
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%v12 = add nsw i32 %v1, 1
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%v13 = icmp slt i32 %v12, %a0
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%v14 = getelementptr i16, i16* %v0, i32 1
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br i1 %v13, label %b2, label %b3
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b3: ; preds = %b2
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unreachable
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b4: ; No predecessors!
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unreachable
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind readnone }
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