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https://github.com/RPCS3/llvm-mirror.git
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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
153 lines
7.6 KiB
LLVM
153 lines
7.6 KiB
LLVM
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}})
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; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.b += v{{[0-9]*}}.b
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; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.b -= v{{[0-9]*}}.b
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; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.h += v{{[0-9]*}}.h
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; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.h -= v{{[0-9]*}}.h
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; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.w += v{{[0-9]*}}.w
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; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.w -= v{{[0-9]*}}.w
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; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.b += v{{[0-9]*}}.b
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; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.b -= v{{[0-9]*}}.b
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; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.h += v{{[0-9]*}}.h
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; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.h -= v{{[0-9]*}}.h
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; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.w += v{{[0-9]*}}.w
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; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.w -= v{{[0-9]*}}.w
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target triple = "hexagon"
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@g0 = common global <16 x i32> zeroinitializer, align 64
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@g1 = common global <16 x i32> zeroinitializer, align 64
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@g2 = common global <16 x i32> zeroinitializer, align 64
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@g3 = common global <16 x i32> zeroinitializer, align 64
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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%v0 = call <16 x i32> @llvm.hexagon.V6.vd0()
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store <16 x i32> %v0, <16 x i32>* @g0, align 64
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%v1 = call <16 x i32> @llvm.hexagon.V6.vd0()
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store <16 x i32> %v1, <16 x i32>* @g1, align 64
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%v2 = call <16 x i32> @llvm.hexagon.V6.vd0()
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store <16 x i32> %v2, <16 x i32>* @g2, align 64
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%v3 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v4 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v3, i32 -1)
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%v5 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v6 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v7 = call <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1> %v4, <16 x i32> %v5, <16 x i32> %v6)
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store <16 x i32> %v7, <16 x i32>* @g2, align 64
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%v8 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v9 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v8, i32 -1)
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%v10 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v11 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v12 = call <16 x i32> @llvm.hexagon.V6.vsubbq(<64 x i1> %v9, <16 x i32> %v10, <16 x i32> %v11)
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store <16 x i32> %v12, <16 x i32>* @g2, align 64
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%v13 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v14 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v13, i32 -1)
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%v15 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v16 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v17 = call <16 x i32> @llvm.hexagon.V6.vaddhq(<64 x i1> %v14, <16 x i32> %v15, <16 x i32> %v16)
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store <16 x i32> %v17, <16 x i32>* @g2, align 64
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%v18 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v19 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v18, i32 -1)
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%v20 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v21 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v22 = call <16 x i32> @llvm.hexagon.V6.vsubhq(<64 x i1> %v19, <16 x i32> %v20, <16 x i32> %v21)
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store <16 x i32> %v22, <16 x i32>* @g2, align 64
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%v23 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v24 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v23, i32 -1)
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%v25 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v26 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v27 = call <16 x i32> @llvm.hexagon.V6.vaddwq(<64 x i1> %v24, <16 x i32> %v25, <16 x i32> %v26)
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store <16 x i32> %v27, <16 x i32>* @g2, align 64
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%v28 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v29 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v28, i32 -1)
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%v30 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v31 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v32 = call <16 x i32> @llvm.hexagon.V6.vsubwq(<64 x i1> %v29, <16 x i32> %v30, <16 x i32> %v31)
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store <16 x i32> %v32, <16 x i32>* @g2, align 64
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%v33 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v34 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v33, i32 -1)
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%v35 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v36 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v37 = call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v34, <16 x i32> %v35, <16 x i32> %v36)
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store <16 x i32> %v37, <16 x i32>* @g2, align 64
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%v38 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v39 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v38, i32 -1)
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%v40 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v41 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v42 = call <16 x i32> @llvm.hexagon.V6.vsubbnq(<64 x i1> %v39, <16 x i32> %v40, <16 x i32> %v41)
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store <16 x i32> %v42, <16 x i32>* @g2, align 64
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%v43 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v44 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v43, i32 -1)
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%v45 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v46 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v47 = call <16 x i32> @llvm.hexagon.V6.vaddhnq(<64 x i1> %v44, <16 x i32> %v45, <16 x i32> %v46)
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store <16 x i32> %v47, <16 x i32>* @g2, align 64
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%v48 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v49 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v48, i32 -1)
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%v50 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v51 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v52 = call <16 x i32> @llvm.hexagon.V6.vsubhnq(<64 x i1> %v49, <16 x i32> %v50, <16 x i32> %v51)
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store <16 x i32> %v52, <16 x i32>* @g2, align 64
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%v53 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v54 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v53, i32 -1)
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%v55 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v56 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v57 = call <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1> %v54, <16 x i32> %v55, <16 x i32> %v56)
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store <16 x i32> %v57, <16 x i32>* @g2, align 64
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%v58 = load <16 x i32>, <16 x i32>* @g3, align 64
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%v59 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v58, i32 -1)
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%v60 = load <16 x i32>, <16 x i32>* @g2, align 64
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%v61 = load <16 x i32>, <16 x i32>* @g1, align 64
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%v62 = call <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1> %v59, <16 x i32> %v60, <16 x i32> %v61)
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store <16 x i32> %v62, <16 x i32>* @g2, align 64
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ret i32 0
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vd0() #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubbq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddhq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubhq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddwq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubwq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubbnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddhnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubhnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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