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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
llvm-mirror/test/CodeGen
Marcin Koscielnicki 8b6548a4bd [SystemZ] Implement backchain attribute (recommit with fix).
This introduces a SystemZ-specific "backchain" attribute on function, which
enables writing the frame backchain link as specified by the ABI.  This will
be used to implement -mbackchain option in clang.

Differential Revision: http://reviews.llvm.org/D19889

Fixed in this version: added RegState::Define and RegState::Kill on R1D
in prologue.

llvm-svn: 268581
2016-05-05 00:37:30 +00:00
..
AArch64 [AArch64] Use the reciprocal estimation machinery 2016-05-04 20:18:27 +00:00
AMDGPU AMDGPU: Custom lower v2i32 loads and stores 2016-05-02 20:13:51 +00:00
ARM Revert r268529 because it caused use-of-uninitialized-value 2016-05-04 19:44:11 +00:00
BPF
CPP
Generic Introduce llvm.load.relative intrinsic. 2016-04-22 21:18:02 +00:00
Hexagon [Hexagon] Optimize addressing modes for load/store 2016-04-29 15:49:13 +00:00
Inputs
Lanai
Mips [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions 2016-05-04 12:02:12 +00:00
MIR ARM: fix handling of SUB immediates in peephole opt. 2016-05-02 18:30:08 +00:00
MSP430
NVPTX [NVPTX] Fix sign/zero-extending ldg/ldu instruction selection 2016-05-02 18:12:02 +00:00
PowerPC [PowerPC] Generate VSX version of splat word 2016-05-04 16:04:02 +00:00
SPARC [Sparc] Allow taking of function address into a register. 2016-05-04 12:11:05 +00:00
SystemZ [SystemZ] Implement backchain attribute (recommit with fix). 2016-05-05 00:37:30 +00:00
Thumb
Thumb2
WebAssembly [WebAssembly] Rename memory_size intrinsic to current_memory 2016-05-02 17:25:22 +00:00
WinEH
X86 [X86] Add a few register classes for x32 address accesses. 2016-05-04 22:45:31 +00:00
XCore