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llvm-mirror/include/llvm/MCA
Andrea Di Biagio 52f56e2249 [MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as depedent. Fixes PR45793.
This fixes a regression introduced by a very old commit 280ac1fd1dc35 (was
llvm-svn 361950).

Commit 280ac1fd1dc35 redesigned the logic in the LSUnit with the goal of
speeding up isReady() queries, and stabilising the LSUnit API (while also making
the load store unit more customisable).

The concept of MemoryGroup (effectively an alias set) was added by that commit
to better describe and track dependencies between memory operations.  However,
that concept was not just used for alias dependencies, but it was also used for
describing memory "order" dependencies (enforced by the memory consistency
model).

Instructions of a same memory group were considered "equivalent" as in:
independent operations that can potentially execute in parallel.  The problem
was that the cost of a dependency (in terms of number of cycles) should have
been different for "order" dependency. Instructions in an order dependency
simply have to have to wait until their predecessors are "issued" to an
underlying pipeline (rather than having to wait until predecessors have beeng
fully executed). For simple "order" dependencies, this was effectively
introducing an artificial delay on the "issue" of independent loads and stores.

This patch fixes the issue and adds a new test named 'independent-load-stores.s'
to a bunch of x86 targets. That test contains the reproducible posted by Fabian
Ritter on PR45793.

I had to rerun the update-mca-tests script on several files. To avoid expected
regressions on some Exynos tests, I have added a -noalias=false flag (to match
the old strict behavior on latencies).

Some tests for processor Barcelona are improved/fixed by this change and they
now show better results.  In a few tests we were incorrectly counting the time
spent by instructions in a scheduler queue.  In one case in particular we now
correctly see a store executed out of order.  That test was affected by the same
underlying issue reported as PR45793.

Reviewers: mattd

Differential Revision: https://reviews.llvm.org/D79351
2020-05-05 10:25:36 +01:00
..
HardwareUnits [MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as depedent. Fixes PR45793. 2020-05-05 10:25:36 +01:00
Stages [llvm-mca] Cleanup unnecessary includes from headers 2020-04-02 11:50:29 +01:00
CodeEmitter.h [llvm-mca] Cleanup unnecessary includes from headers 2020-04-02 11:50:29 +01:00
Context.h [MCA] Remove dependency from InstrBuilder in mca::Context. NFC 2019-08-08 10:30:58 +00:00
HWEventListener.h [MCA] Notify event listeners when instructions transition to the Pending state. NFCI 2019-05-05 16:07:27 +00:00
InstrBuilder.h
Instruction.h [MCA] consistently use MCPhysReg instead of unsigned as register type. NFCI 2019-08-22 13:32:17 +00:00
Pipeline.h [llvm-mca] Cleanup unnecessary includes from headers 2020-04-02 11:50:29 +01:00
SourceMgr.h [MCA] Fix MSVC 19.16 build with libc++ 2019-08-09 12:41:24 +00:00
Support.h