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d73d332555
v2: added more tests, moved the SALU->VALU conversion to a separate function It looks like it's not possible to get subregisters in the S_ABS lowering code, and I don't feel like guessing without testing what the correct code would look like. llvm-svn: 254095
48 lines
1.5 KiB
LLVM
48 lines
1.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare i32 @llvm.AMDGPU.abs(i32) nounwind readnone
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; Legacy name
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declare i32 @llvm.AMDIL.abs.i32(i32) nounwind readnone
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; FUNC-LABEL: {{^}}s_abs_i32:
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; SI: s_abs_i32
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; EG: SUB_INT
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; EG: MAX_INT
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define void @s_abs_i32(i32 addrspace(1)* %out, i32 %src) nounwind {
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%abs = call i32 @llvm.AMDGPU.abs(i32 %src) nounwind readnone
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store i32 %abs, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_abs_i32:
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; SI: v_sub_i32_e32
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; SI: v_max_i32_e32
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; SI: s_endpgm
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; EG: SUB_INT
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; EG: MAX_INT
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define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
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%val = load i32, i32 addrspace(1)* %src, align 4
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%abs = call i32 @llvm.AMDGPU.abs(i32 %val) nounwind readnone
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store i32 %abs, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}abs_i32_legacy_amdil:
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; SI: v_sub_i32_e32
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; SI: v_max_i32_e32
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; SI: s_endpgm
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; EG: SUB_INT
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; EG: MAX_INT
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define void @abs_i32_legacy_amdil(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
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%val = load i32, i32 addrspace(1)* %src, align 4
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%abs = call i32 @llvm.AMDIL.abs.i32(i32 %val) nounwind readnone
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store i32 %abs, i32 addrspace(1)* %out, align 4
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ret void
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}
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