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https://github.com/RPCS3/llvm-mirror.git
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cdae83c48c
Re-comitting with a change that avoids undefined uses getting put into the VRegUses list. The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254683
270 lines
8.7 KiB
LLVM
270 lines
8.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=HSA -check-prefix=CI-HSA -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=HSA -check-prefix=VI-HSA -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}ngroups_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].X
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; HSA: .amd_kernel_code_t
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: enable_sgpr_dispatch_id = 0
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; HSA: enable_sgpr_flat_scratch_init = 0
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; HSA: enable_sgpr_private_segment_size = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; HSA: .end_amd_kernel_code_t
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; GCN-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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define void @ngroups_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ngroups_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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define void @ngroups_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ngroups_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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define void @ngroups_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].W
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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define void @global_size_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[1].X
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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define void @global_size_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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define void @global_size_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; The tgid values are stored in sgprs offset by the number of user
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; sgprs.
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; FUNC-LABEL: {{^}}tgid_x:
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; HSA: .amd_kernel_code_t
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 0
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; HSA: compute_pgm_rsrc2_tgid_z_en = 0
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; HSA: .end_amd_kernel_code_t
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s2{{$}}
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; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s6{{$}}
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; GCN: buffer_store_dword [[VVAL]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @tgid_x(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tgid_y:
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 1
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; HSA: compute_pgm_rsrc2_tgid_z_en = 0
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3
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; GCN-HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s7
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; GCN: buffer_store_dword [[VVAL]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
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; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @tgid_y(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}tgid_z:
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 0
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; HSA: compute_pgm_rsrc2_tgid_z_en = 1
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: enable_sgpr_dispatch_id = 0
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; HSA: enable_sgpr_flat_scratch_init = 0
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; HSA: enable_sgpr_private_segment_size = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3{{$}}
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; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s7{{$}}
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; GCN: buffer_store_dword [[VVAL]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
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; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @tgid_z(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-NOHSA: .section .AMDGPU.config
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; GCN-NOHSA: .long 47180
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; GCN-NOHSA-NEXT: .long 132{{$}}
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; FUNC-LABEL: {{^}}tidig_x:
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; GCN: buffer_store_dword v0
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define void @tidig_x(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-NOHSA: .section .AMDGPU.config
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; GCN-NOHSA: .long 47180
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; GCN-NOHSA-NEXT: .long 2180{{$}}
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; FUNC-LABEL: {{^}}tidig_y:
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 1
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; GCN: buffer_store_dword v1
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define void @tidig_y(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-NOHSA: .section .AMDGPU.config
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; GCN-NOHSA: .long 47180
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; GCN-NOHSA-NEXT: .long 4228{{$}}
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; FUNC-LABEL: {{^}}tidig_z:
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 2
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; GCN: buffer_store_dword v2
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define void @tidig_z(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.ngroups.x() #0
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declare i32 @llvm.r600.read.ngroups.y() #0
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declare i32 @llvm.r600.read.ngroups.z() #0
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declare i32 @llvm.r600.read.global.size.x() #0
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declare i32 @llvm.r600.read.global.size.y() #0
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declare i32 @llvm.r600.read.global.size.z() #0
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declare i32 @llvm.r600.read.tgid.x() #0
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declare i32 @llvm.r600.read.tgid.y() #0
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declare i32 @llvm.r600.read.tgid.z() #0
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declare i32 @llvm.r600.read.tidig.x() #0
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declare i32 @llvm.r600.read.tidig.y() #0
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declare i32 @llvm.r600.read.tidig.z() #0
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declare i32 @llvm.AMDGPU.read.workdim() #0
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attributes #0 = { readnone }
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