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e3114ca1df
Summary: Setting MIMG to 0 has a bunch of unexpected side effects, including that isVMEM returns false which leads to incorrect treatment in the hazard recognizer. The reason I noticed it is that it also leads to incorrect treatment in VGPR-to-SGPR copies, which is one cause of the referenced bug. The only reason why MIMG was set to 0 is to signal the special handling of dmasks, but that can be checked differently. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96877 Reviewers: arsenm, tstellarAMD Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D22210 llvm-svn: 275113
579 lines
19 KiB
C++
579 lines
19 KiB
C++
//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIDefines.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIInstrInfo final : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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const SISubtarget &ST;
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// The the inverse predicate should have the negative value.
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enum BranchPredicate {
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INVALID_BR = 0,
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SCC_TRUE = 1,
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SCC_FALSE = -1,
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VCCNZ = 2,
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VCCZ = -2,
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EXECNZ = -3,
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EXECZ = 3
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};
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static unsigned getBranchOpcode(BranchPredicate Cond);
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static BranchPredicate getBranchPredicate(unsigned Opcode);
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unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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void swapOperands(MachineInstr &Inst) const;
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void lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr &Inst) const;
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void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr &Inst, unsigned Opcode) const;
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void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr &Inst, unsigned Opcode) const;
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void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr &Inst) const;
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void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr &Inst) const;
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void addUsersToMoveToVALUWorklist(
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unsigned Reg, MachineRegisterInfo &MRI,
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SmallVectorImpl<MachineInstr *> &Worklist) const;
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void
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addSCCDefUsersToVALUWorklist(MachineInstr &SCCDefInst,
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SmallVectorImpl<MachineInstr *> &Worklist) const;
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const TargetRegisterClass *
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getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
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bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
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unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
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protected:
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx0,
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unsigned OpIdx1) const override;
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public:
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explicit SIInstrInfo(const SISubtarget &);
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const SIRegisterInfo &getRegisterInfo() const {
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return RI;
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}
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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AliasAnalysis *AA) const override;
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bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1,
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int64_t &Offset2) const override;
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bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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int64_t &Offset,
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const TargetRegisterInfo *TRI) const final;
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bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
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unsigned NumLoads) const final;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
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RegScavenger *RS, unsigned TmpReg,
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unsigned Offset, unsigned Size) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, unsigned SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, unsigned DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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// \brief Returns an opcode that can be used to move a value to a \p DstRC
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// register. If there is no hardware instruction that can store to \p
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// DstRC, then AMDGPU::COPY is returned.
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unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
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LLVM_READONLY
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int commuteOpcode(const MachineInstr &MI) const;
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bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL) const override;
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bool ReverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const override;
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bool
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areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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AliasAnalysis *AA = nullptr) const override;
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bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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MachineRegisterInfo *MRI) const final;
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unsigned getMachineCSELookAheadLimit() const override { return 500; }
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MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
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MachineInstr &MI,
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LiveVariables *LV) const override;
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bool isSchedulingBoundary(const MachineInstr &MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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static bool isSALU(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SALU;
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}
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bool isSALU(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SALU;
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}
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static bool isVALU(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VALU;
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}
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bool isVALU(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VALU;
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}
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static bool isVMEM(const MachineInstr &MI) {
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return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
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}
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bool isVMEM(uint16_t Opcode) const {
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return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
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}
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static bool isSOP1(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
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}
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bool isSOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOP1;
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}
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static bool isSOP2(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
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}
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bool isSOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOP2;
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}
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static bool isSOPC(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
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}
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bool isSOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPC;
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}
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static bool isSOPK(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
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}
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bool isSOPK(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPK;
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}
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static bool isSOPP(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
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}
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bool isSOPP(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPP;
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}
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static bool isVOP1(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
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}
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bool isVOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP1;
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}
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static bool isVOP2(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
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}
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bool isVOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP2;
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}
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static bool isVOP3(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
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}
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bool isVOP3(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP3;
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}
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static bool isVOPC(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
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}
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bool isVOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOPC;
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}
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static bool isMUBUF(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
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}
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bool isMUBUF(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
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}
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static bool isMTBUF(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
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}
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bool isMTBUF(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
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}
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static bool isSMRD(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
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}
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bool isSMRD(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SMRD;
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}
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static bool isDS(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::DS;
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}
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bool isDS(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::DS;
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}
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static bool isMIMG(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
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}
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bool isMIMG(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MIMG;
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}
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static bool isGather4(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
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}
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bool isGather4(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::Gather4;
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}
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static bool isFLAT(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
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}
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bool isFLAT(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::FLAT;
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}
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static bool isWQM(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::WQM;
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}
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bool isWQM(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::WQM;
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}
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static bool isVGPRSpill(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
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}
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bool isVGPRSpill(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
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}
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static bool isDPP(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::DPP;
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}
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bool isDPP(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::DPP;
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}
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bool isVGPRCopy(const MachineInstr &MI) const {
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assert(MI.isCopy());
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unsigned Dest = MI.getOperand(0).getReg();
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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return !RI.isSGPRReg(MRI, Dest);
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}
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bool isInlineConstant(const APInt &Imm) const;
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bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
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bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
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bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
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const MachineOperand &MO) const;
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/// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
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/// This function will return false if you pass it a 32-bit instruction.
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bool hasVALU32BitEncoding(unsigned Opcode) const;
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/// \brief Returns true if this operand uses the constant bus.
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bool usesConstantBus(const MachineRegisterInfo &MRI,
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const MachineOperand &MO,
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unsigned OpSize) const;
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/// \brief Return true if this instruction has any modifiers.
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/// e.g. src[012]_mod, omod, clamp.
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bool hasModifiers(unsigned Opcode) const;
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bool hasModifiersSet(const MachineInstr &MI,
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unsigned OpName) const;
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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static unsigned getVALUOp(const MachineInstr &MI);
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bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
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/// \brief Return the correct register class for \p OpNo. For target-specific
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/// instructions, this will return the register class that has been defined
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/// in tablegen. For generic instructions, like REG_SEQUENCE it will return
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/// the register class of its machine operand.
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/// to infer the correct register class base on the other operands.
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const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
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unsigned OpNo) const;
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/// \brief Return the size in bytes of the operand OpNo on the given
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// instruction opcode.
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unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
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const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
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if (OpInfo.RegClass == -1) {
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// If this is an immediate operand, this must be a 32-bit literal.
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assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
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return 4;
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}
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return RI.getRegClass(OpInfo.RegClass)->getSize();
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}
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/// \brief This form should usually be preferred since it handles operands
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/// with unknown register classes.
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unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
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return getOpRegClass(MI, OpNo)->getSize();
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}
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/// \returns true if it is legal for the operand at index \p OpNo
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/// to read a VGPR.
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bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
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/// \brief Legalize the \p OpIndex operand of this instruction by inserting
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/// a MOV. For example:
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/// ADD_I32_e32 VGPR0, 15
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/// to
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/// MOV VGPR1, 15
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/// ADD_I32_e32 VGPR0, VGPR1
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///
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/// If the operand being legalized is a register, then a COPY will be used
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/// instead of MOV.
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void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
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/// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
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/// for \p MI.
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bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
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const MachineOperand *MO = nullptr) const;
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/// \brief Check if \p MO would be a valid operand for the given operand
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/// definition \p OpInfo. Note this does not attempt to validate constant bus
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/// restrictions (e.g. literal constant usage).
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bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
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const MCOperandInfo &OpInfo,
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const MachineOperand &MO) const;
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/// \brief Check if \p MO (a register operand) is a legal register for the
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/// given operand description.
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bool isLegalRegOperand(const MachineRegisterInfo &MRI,
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const MCOperandInfo &OpInfo,
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const MachineOperand &MO) const;
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/// \brief Legalize operands in \p MI by either commuting it or inserting a
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/// copy of src1.
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void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
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/// \brief Fix operands in \p MI to satisfy constant bus requirements.
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void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
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/// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
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/// be used when it is know that the value in SrcReg is same across all
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/// threads in the wave.
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/// \returns The SGPR register that \p SrcReg was copied to.
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unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
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MachineRegisterInfo &MRI) const;
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void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
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/// \brief Legalize all operands in this instruction. This function may
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/// create new instruction and insert them before \p MI.
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void legalizeOperands(MachineInstr &MI) const;
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/// \brief Replace this instruction's opcode with the equivalent VALU
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/// opcode. This function will also move the users of \p MI to the
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/// VALU if necessary.
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void moveToVALU(MachineInstr &MI) const;
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void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
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int Count) const;
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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/// \brief Return the number of wait states that result from executing this
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/// instruction.
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unsigned getNumWaitStates(const MachineInstr &MI) const;
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/// \brief Returns the operand named \p Op. If \p MI does not have an
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/// operand named \c Op, this function returns nullptr.
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LLVM_READONLY
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MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
|
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LLVM_READONLY
|
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const MachineOperand *getNamedOperand(const MachineInstr &MI,
|
|
unsigned OpName) const {
|
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return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
|
|
}
|
|
|
|
/// Get required immediate operand
|
|
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
|
|
int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
|
|
return MI.getOperand(Idx).getImm();
|
|
}
|
|
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|
uint64_t getDefaultRsrcDataFormat() const;
|
|
uint64_t getScratchRsrcWords23() const;
|
|
|
|
bool isLowLatencyInstruction(const MachineInstr &MI) const;
|
|
bool isHighLatencyInstruction(const MachineInstr &MI) const;
|
|
|
|
/// \brief Return the descriptor of the target-specific machine instruction
|
|
/// that corresponds to the specified pseudo or native opcode.
|
|
const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
|
|
return get(pseudoToMCOpcode(Opcode));
|
|
}
|
|
|
|
unsigned getInstSizeInBytes(const MachineInstr &MI) const;
|
|
|
|
ArrayRef<std::pair<int, const char *>>
|
|
getSerializableTargetIndices() const override;
|
|
|
|
ScheduleHazardRecognizer *
|
|
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
|
|
const ScheduleDAG *DAG) const override;
|
|
|
|
ScheduleHazardRecognizer *
|
|
CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
|
|
};
|
|
|
|
namespace AMDGPU {
|
|
LLVM_READONLY
|
|
int getVOPe64(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getVOPe32(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getCommuteRev(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getCommuteOrig(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getAddr64Inst(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getAtomicRetOp(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getAtomicNoRetOp(uint16_t Opcode);
|
|
|
|
const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
|
|
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
|
|
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
|
|
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
|
|
} // End namespace AMDGPU
|
|
|
|
namespace SI {
|
|
namespace KernelInputOffsets {
|
|
|
|
/// Offsets in bytes from the start of the input buffer
|
|
enum Offsets {
|
|
NGROUPS_X = 0,
|
|
NGROUPS_Y = 4,
|
|
NGROUPS_Z = 8,
|
|
GLOBAL_SIZE_X = 12,
|
|
GLOBAL_SIZE_Y = 16,
|
|
GLOBAL_SIZE_Z = 20,
|
|
LOCAL_SIZE_X = 24,
|
|
LOCAL_SIZE_Y = 28,
|
|
LOCAL_SIZE_Z = 32
|
|
};
|
|
|
|
} // End namespace KernelInputOffsets
|
|
} // End namespace SI
|
|
|
|
} // End namespace llvm
|
|
|
|
#endif
|