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583 lines
26 KiB
C++
583 lines
26 KiB
C++
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86ISELLOWERING_H
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#define X86ISELLOWERING_H
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#include "X86Subtarget.h"
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#include "X86RegisterInfo.h"
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#include "X86MachineFunctionInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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namespace llvm {
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namespace X86ISD {
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// X86 Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
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/// BSF - Bit scan forward.
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/// BSR - Bit scan reverse.
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BSF,
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BSR,
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/// SHLD, SHRD - Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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SHRD,
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/// FAND - Bitwise logical AND of floating point values. This corresponds
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/// to X86::ANDPS or X86::ANDPD.
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FAND,
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/// FOR - Bitwise logical OR of floating point values. This corresponds
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/// to X86::ORPS or X86::ORPD.
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FOR,
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/// FXOR - Bitwise logical XOR of floating point values. This corresponds
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/// to X86::XORPS or X86::XORPD.
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FXOR,
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/// FSRL - Bitwise logical right shift of floating point values. These
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/// corresponds to X86::PSRLDQ.
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FSRL,
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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/// also produces a flag).
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FILD,
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FILD_FLAG,
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/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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/// has two inputs (token chain and address) and two outputs (int value
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/// and token chain).
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// CALL/TAILCALL - These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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///
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/// #0 - The incoming token chain
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/// #1 - The callee
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/// #2 - The number of arg bytes the caller pushes on the stack.
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/// #3 - The number of arg bytes the callee pops off the stack.
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/// #4 - The value to pass in AL/AX/EAX (optional)
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/// #5 - The value to pass in DL/DX/EDX (optional)
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///
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/// The result values of these nodes are:
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///
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/// #0 - The outgoing token chain
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/// #1 - The first register result value (optional)
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/// #2 - The second register result value (optional)
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///
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/// The CALL vs TAILCALL distinction boils down to whether the callee is
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/// known not to modify the caller's stack frame, as is standard with
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/// LLVM.
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CALL,
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TAILCALL,
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/// RDTSC_DAG - This operation implements the lowering for
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/// readcyclecounter
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RDTSC_DAG,
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/// X86 compare and logical compare instructions.
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CMP, COMI, UCOMI,
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/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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/// X86 conditional moves. Operand 1 and operand 2 are the two values
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/// to select from (operand 1 is a R/W operand). Operand 3 is the
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/// condition code, and operand 4 is the flag operand produced by a CMP
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/// or TEST instruction. It also writes a flag result.
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CMOV,
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/// X86 conditional branches. Operand 1 is the chain operand, operand 2
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/// is the block to branch if condition is true, operand 3 is the
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/// condition code, and operand 4 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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/// Return with a flag operand. Operand 1 is the chain operand, operand
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/// 2 is the number of bytes of stack to pop.
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RET_FLAG,
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/// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
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REP_STOS,
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/// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
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REP_MOVS,
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/// GlobalBaseReg - On Darwin, this node represents the result of the popl
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// Wrapper - A wrapper node for TargetConstantPool,
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/// TargetExternalSymbol, and TargetGlobalAddress.
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Wrapper,
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/// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
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/// relative displacements.
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WrapperRIP,
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/// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRB.
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PEXTRB,
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/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRW.
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PEXTRW,
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/// INSERTPS - Insert any element of a 4 x float vector into any element
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/// of a destination 4 x floatvector.
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INSERTPS,
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/// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRB.
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PINSRB,
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/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRW.
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PINSRW,
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/// FMAX, FMIN - Floating point max and min.
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///
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FMAX, FMIN,
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/// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
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/// approximation. Note that these typically require refinement
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/// in order to obtain suitable precision.
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FRSQRT, FRCP,
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// TLSADDR, THREAThread - Thread Local Storage.
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TLSADDR, THREAD_POINTER,
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// EH_RETURN - Exception Handling helpers.
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EH_RETURN,
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/// TC_RETURN - Tail call return.
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/// operand #0 chain
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/// operand #1 callee (register or absolute)
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/// operand #2 stack adjustment
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/// operand #3 optional in flag
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TC_RETURN,
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// LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
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LCMPXCHG_DAG,
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LCMPXCHG8_DAG,
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// FNSTCW16m - Store FP control world into i16 memory.
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FNSTCW16m,
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// VZEXT_MOVL - Vector move low and zero extend.
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VZEXT_MOVL,
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// VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
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VZEXT_LOAD,
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// VSHL, VSRL - Vector logical left / right shift.
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VSHL, VSRL
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};
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}
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/// Define some predicates that are used for node matching.
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namespace X86 {
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFDMask(SDNode *N);
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/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFHWMask(SDNode *N);
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/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFLWMask(SDNode *N);
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to SHUFP*.
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bool isSHUFPMask(SDNode *N);
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/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
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bool isMOVHLPSMask(SDNode *N);
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/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
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/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
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/// <2, 3, 2, 3>
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bool isMOVHLPS_v_undef_Mask(SDNode *N);
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/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
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bool isMOVLPMask(SDNode *N);
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/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
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/// as well as MOVLHPS.
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bool isMOVHPMask(SDNode *N);
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/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKL.
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bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
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/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKH.
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bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
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/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
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/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
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/// <0, 0, 1, 1>
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bool isUNPCKL_v_undef_Mask(SDNode *N);
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/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
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/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
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/// <2, 2, 3, 3>
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bool isUNPCKH_v_undef_Mask(SDNode *N);
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/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSS,
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/// MOVSD, and MOVD, i.e. setting the lowest element.
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bool isMOVLMask(SDNode *N);
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
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bool isMOVSHDUPMask(SDNode *N);
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/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
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bool isMOVSLDUPMask(SDNode *N);
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element.
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bool isSplatMask(SDNode *N);
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/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of zero element.
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bool isSplatLoMask(SDNode *N);
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/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
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/// instructions.
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unsigned getShuffleSHUFImmediate(SDNode *N);
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/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
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/// instructions.
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unsigned getShufflePSHUFHWImmediate(SDNode *N);
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/// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
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/// instructions.
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unsigned getShufflePSHUFLWImmediate(SDNode *N);
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}
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//===--------------------------------------------------------------------===//
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// X86TargetLowering - X86 Implementation of the TargetLowering interface
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class X86TargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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int RegSaveFrameIndex; // X86-64 vararg func register save area.
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unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
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unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
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int BytesToPopOnReturn; // Number of arg bytes ret should pop.
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int BytesCallerReserves; // Number of arg bytes caller makes.
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public:
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explicit X86TargetLowering(X86TargetMachine &TM);
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/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
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/// jumptable.
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SDOperand getPICJumpTableRelocBase(SDOperand Table,
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SelectionDAG &DAG) const;
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// Return the number of bytes that a function should pop when it returns (in
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// addition to the space used by the return address).
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//
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unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
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// Return the number of bytes that the caller reserves for arguments passed
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// to this function.
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unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
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/// getStackPtrReg - Return the stack pointer register we are using: either
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/// ESP or RSP.
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unsigned getStackPtrReg() const { return X86StackPtr; }
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/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
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/// function arguments in the caller parameter area. For X86, aggregates
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/// that contains are placed at 16-byte boundaries while the rest are at
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/// 4-byte boundaries.
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virtual unsigned getByValTypeAlignment(const Type *Ty) const;
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/// getOptimalMemOpType - Returns the target specific optimal type for load
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/// and store operations as a result of memset, memcpy, and memmove
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/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
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/// determining it.
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virtual
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MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
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bool isSrcConst, bool isSrcStr) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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/// ExpandOperation - Custom lower the specified operation, splitting the
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/// value into two pieces.
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///
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virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
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virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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virtual MVT getSetCCResultType(const SDOperand &) const;
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified
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/// in Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
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const APInt &Mask,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual bool
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isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
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SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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virtual const char *LowerXConstraint(MVT ConstraintVT) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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virtual void LowerAsmOperandForConstraint(SDOperand Op,
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char ConstraintLetter,
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std::vector<SDOperand> &Ops,
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SelectionDAG &DAG) const;
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/// getRegForInlineAsmConstraint - Given a physical register constraint
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/// (e.g. {edx}), return the register number and the register class for the
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/// register. This should only be used for C_Register constraints. On
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/// error, this returns a register number of 0.
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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/// isTruncateFree - Return true if it's free to truncate a value of
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/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
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/// register EAX to i16 by referencing its sub-register AX.
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virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
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virtual bool isTruncateFree(MVT VT1, MVT VT2) const;
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
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/// values are assumed to be legal.
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virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const;
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/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
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/// used by Targets can use this to indicate if there is a suitable
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/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
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/// pool entry.
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virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
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MVT EVT, SelectionDAG &DAG) const;
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/// ShouldShrinkFPConstant - If true, then instruction selection should
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/// seek to shrink the FP constant of the specified type to a smaller type
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/// in order to save space and / or reduce runtime.
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virtual bool ShouldShrinkFPConstant(MVT VT) const {
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// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
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// expensive than a straight movsd. On the other hand, it's important to
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// shrink long double fp constant since fldt is very slow.
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return !X86ScalarSSEf64 || VT == MVT::f80;
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}
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization. Target which want to do tail call
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/// optimization should implement this function.
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virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
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SDOperand Ret,
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SelectionDAG &DAG) const;
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virtual const X86Subtarget* getSubtarget() {
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return Subtarget;
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}
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/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
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/// computed in an SSE register, not on the X87 floating point stack.
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bool isScalarFPTypeInSSEReg(MVT VT) const {
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return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
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(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
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}
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private:
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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const X86RegisterInfo *RegInfo;
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/// X86StackPtr - X86 physical register used as stack ptr.
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unsigned X86StackPtr;
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/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
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/// floating point ops.
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/// When SSE is available, use it for f32 operations.
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/// When SSE2 is available, use it for f64 operations.
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bool X86ScalarSSEf32;
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bool X86ScalarSSEf64;
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SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
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unsigned CallingConv, SelectionDAG &DAG);
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SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
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const CCValAssign &VA, MachineFrameInfo *MFI,
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unsigned CC, SDOperand Root, unsigned i);
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SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
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const SDOperand &StackPtr,
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const CCValAssign &VA, SDOperand Chain,
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SDOperand Arg);
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// Call lowering helpers.
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bool IsCalleePop(SDOperand Op);
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bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall);
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bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
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SDOperand EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDOperand &OutRetAddr,
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SDOperand Chain, bool IsTailCall, bool Is64Bit,
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int FPDiff);
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CCAssignFn *CCAssignFnForNode(SDOperand Op) const;
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NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op);
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unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
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std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
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SelectionDAG &DAG);
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SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
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|
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
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|
SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
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|
SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG);
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|
SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
|
|
SDOperand LowerLCS(SDOperand Op, SelectionDAG &DAG);
|
|
SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
|
|
SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
|
|
SDNode *ExpandATOMIC_LCS(SDNode *N, SelectionDAG &DAG);
|
|
SDNode *ExpandATOMIC_LSS(SDNode *N, SelectionDAG &DAG);
|
|
|
|
SDOperand EmitTargetCodeForMemset(SelectionDAG &DAG,
|
|
SDOperand Chain,
|
|
SDOperand Dst, SDOperand Src,
|
|
SDOperand Size, unsigned Align,
|
|
const Value *DstSV, uint64_t DstSVOff);
|
|
SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
|
|
SDOperand Chain,
|
|
SDOperand Dst, SDOperand Src,
|
|
SDOperand Size, unsigned Align,
|
|
bool AlwaysInline,
|
|
const Value *DstSV, uint64_t DstSVOff,
|
|
const Value *SrcSV, uint64_t SrcSVOff);
|
|
|
|
/// Utility function to emit atomic bitwise operations (and, or, xor).
|
|
// It takes the bitwise instruction to expand, the associated machine basic
|
|
// block, and the associated X86 opcodes for reg/reg and reg/imm.
|
|
MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
|
|
MachineInstr *BInstr,
|
|
MachineBasicBlock *BB,
|
|
unsigned regOpc,
|
|
unsigned immOpc,
|
|
bool invSrc = false);
|
|
|
|
/// Utility function to emit atomic min and max. It takes the min/max
|
|
// instruction to expand, the associated basic block, and the associated
|
|
// cmov opcode for moving the min or max value.
|
|
MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
|
|
MachineBasicBlock *BB,
|
|
unsigned cmovOpc);
|
|
};
|
|
}
|
|
|
|
#endif // X86ISELLOWERING_H
|