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bc3e25486a
The new names for FPRs ensure that the Register values within the same class are enumerated consecutively (the order is determined by the `LessRecordRegister` function object). Where there were tables mapping between 32- and 64-bit FPRs (and vice versa) this patch replaces them with Register arithmetic. The enumeration order between different register classes is expected to continue to be arbitrary, although it does impact the conversion from the (overloaded) asm FPR names to Register values, and therefore might require updates to the target if the sorting algorithm is changed. Static asserts were added to ensure that changes to the ordering that would impact the current implementation are detected. Differential Revision: https://reviews.llvm.org/D67423 llvm-svn: 373096
66 lines
2.3 KiB
TableGen
66 lines
2.3 KiB
TableGen
//===-- RISCVCallingConv.td - Calling Conventions RISCV ----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the RISCV architecture.
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//
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//===----------------------------------------------------------------------===//
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// The RISC-V calling convention is handled with custom code in
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// RISCVISelLowering.cpp (CC_RISCV).
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def CSR_ILP32_LP64
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: CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
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def CSR_ILP32F_LP64F
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: CalleeSavedRegs<(add CSR_ILP32_LP64,
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F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
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def CSR_ILP32D_LP64D
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: CalleeSavedRegs<(add CSR_ILP32_LP64,
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F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
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// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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// Interrupt handler needs to save/restore all registers that are used,
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// both Caller and Callee saved registers.
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def CSR_Interrupt : CalleeSavedRegs<(add X1,
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(sequence "X%u", 3, 9),
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(sequence "X%u", 10, 11),
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(sequence "X%u", 12, 17),
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(sequence "X%u", 18, 27),
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(sequence "X%u", 28, 31))>;
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// Same as CSR_Interrupt, but including all 32-bit FP registers.
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def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
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(sequence "X%u", 3, 9),
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(sequence "X%u", 10, 11),
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(sequence "X%u", 12, 17),
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(sequence "X%u", 18, 27),
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(sequence "X%u", 28, 31),
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(sequence "F%u_F", 0, 7),
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(sequence "F%u_F", 10, 11),
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(sequence "F%u_F", 12, 17),
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(sequence "F%u_F", 28, 31),
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(sequence "F%u_F", 8, 9),
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(sequence "F%u_F", 18, 27))>;
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// Same as CSR_Interrupt, but including all 64-bit FP registers.
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def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
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(sequence "X%u", 3, 9),
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(sequence "X%u", 10, 11),
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(sequence "X%u", 12, 17),
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(sequence "X%u", 18, 27),
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(sequence "X%u", 28, 31),
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(sequence "F%u_D", 0, 7),
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(sequence "F%u_D", 10, 11),
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(sequence "F%u_D", 12, 17),
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(sequence "F%u_D", 28, 31),
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(sequence "F%u_D", 8, 9),
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(sequence "F%u_D", 18, 27))>;
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