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0536ef1194
These patterns are using zexti32 which matches either assertzexti32 or (and X, 0xffffffff). But if we match (and X, 0xffffffff) it will remove the AND and the inputs may no longer have the zero bits needed to guarantee the result has enough zeros. This commit changes the patterns to only match assertzexti32. I'm not sure how to test the broken case since the DIVUW/REMUW nodes are created during type legalization, but type legalization won't create an (and X, 0xfffffffff) directly on the inputs. I've also changed the zexti32 on the root of the pattern to just checking for AND. We were previously also matching assertzexti32, but I doubt that pattern would ever occur.
100 lines
4.3 KiB
TableGen
100 lines
4.3 KiB
TableGen
//===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'M', Integer
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// Multiplication and Division instruction set extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def riscv_divw : SDNode<"RISCVISD::DIVW", SDTIntBinOp>;
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def riscv_divuw : SDNode<"RISCVISD::DIVUW", SDTIntBinOp>;
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def riscv_remuw : SDNode<"RISCVISD::REMUW", SDTIntBinOp>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtM] in {
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def MUL : ALU_rr<0b0000001, 0b000, "mul">,
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Sched<[WriteIMul, ReadIMul, ReadIMul]>;
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def MULH : ALU_rr<0b0000001, 0b001, "mulh">,
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Sched<[WriteIMul, ReadIMul, ReadIMul]>;
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def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
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Sched<[WriteIMul, ReadIMul, ReadIMul]>;
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def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">,
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Sched<[WriteIMul, ReadIMul, ReadIMul]>;
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def DIV : ALU_rr<0b0000001, 0b100, "div">,
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Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
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def DIVU : ALU_rr<0b0000001, 0b101, "divu">,
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Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
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def REM : ALU_rr<0b0000001, 0b110, "rem">,
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Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
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def REMU : ALU_rr<0b0000001, 0b111, "remu">,
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Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
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} // Predicates = [HasStdExtM]
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let Predicates = [HasStdExtM, IsRV64] in {
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def MULW : ALUW_rr<0b0000001, 0b000, "mulw">,
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Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
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def DIVW : ALUW_rr<0b0000001, 0b100, "divw">,
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Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
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def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">,
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Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
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def REMW : ALUW_rr<0b0000001, 0b110, "remw">,
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Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
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def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">,
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Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
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} // Predicates = [HasStdExtM, IsRV64]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtM] in {
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def : PatGprGpr<mul, MUL>;
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def : PatGprGpr<mulhs, MULH>;
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def : PatGprGpr<mulhu, MULHU>;
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// No ISDOpcode for mulhsu
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def : PatGprGpr<sdiv, DIV>;
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def : PatGprGpr<udiv, DIVU>;
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def : PatGprGpr<srem, REM>;
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def : PatGprGpr<urem, REMU>;
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} // Predicates = [HasStdExtM]
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let Predicates = [HasStdExtM, IsRV64] in {
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def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
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(MULW GPR:$rs1, GPR:$rs2)>;
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def : PatGprGpr<riscv_divw, DIVW>;
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def : PatGprGpr<riscv_divuw, DIVUW>;
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def : PatGprGpr<riscv_remuw, REMUW>;
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// Handle the specific cases where using DIVU/REMU would be correct and result
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// in fewer instructions than emitting DIVUW/REMUW then zero-extending the
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// result.
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def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
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(assertzexti32 GPR:$rs2)), 0xffffffff),
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(DIVU GPR:$rs1, GPR:$rs2)>;
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def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
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(assertzexti32 GPR:$rs2)), 0xffffffff),
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(REMU GPR:$rs1, GPR:$rs2)>;
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// Although the sexti32 operands may not have originated from an i32 srem,
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// this pattern is safe as it is impossible for two sign extended inputs to
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// produce a result where res[63:32]=0 and res[31]=1.
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def : Pat<(srem (sexti32 GPR:$rs1), (sexti32 GPR:$rs2)),
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(REMW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(sext_inreg (srem (sexti32 GPR:$rs1),
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(sexti32 GPR:$rs2)), i32),
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(REMW GPR:$rs1, GPR:$rs2)>;
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} // Predicates = [HasStdExtM, IsRV64]
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