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db43217a24
Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
74 lines
2.3 KiB
LLVM
74 lines
2.3 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; Function Attrs: nounwind
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; Check that we accept 'U' and 'X' constraints.
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; Generated from following C code:
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;
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; void foo (int result, char *addr) {
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; __asm__ __volatile__ (
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; "ld%U1%X1 %0,%1\n"
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; "cmpw %0,%0\n"
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; "bne- 1f\n"
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; "1: isync\n"
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; : "=r" (result)
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; : "m"(*addr) : "memory", "cr0");
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; }
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define void @foo(i32 signext %result, i8* %addr) #0 {
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; CHECK-LABEL: @foo
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; CHECK: ld [[REG:[0-9]+]], 0(4)
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; CHECK: cmpw [[REG]], [[REG]]
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; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]]
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; CHECK: .Ltmp[[TMP]]:
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; CHECK: isync
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entry:
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%result.addr = alloca i32, align 4
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%addr.addr = alloca i8*, align 8
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store i32 %result, i32* %result.addr, align 4
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store i8* %addr, i8** %addr.addr, align 8
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%0 = load i8*, i8** %addr.addr, align 8
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%1 = call i32 asm sideeffect "ld${1:U}${1:X} $0,$1\0Acmpw $0,$0\0Abne- 1f\0A1: isync\0A", "=r,*m,~{memory},~{cr0}"(i8* %0) #1, !srcloc !0
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store i32 %1, i32* %result.addr, align 4
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ret void
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}
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; Function Attrs: nounwind
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; Check that we accept the 'd' constraint.
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; Generated from the following C code:
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; int foo(double x) {
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; int64_t result;
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; __asm__ __volatile__("fctid %0, %1"
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; : "=d"(result)
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; : "d"(x)
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; : /* No clobbers */);
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; return result;
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; }
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define signext i32 @bar(double %x) #0 {
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; CHECK-LABEL: @bar
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; CHECK: fctid 0, 1
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entry:
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%x.addr = alloca double, align 8
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%result = alloca i64, align 8
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store double %x, double* %x.addr, align 8
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%0 = load double, double* %x.addr, align 8
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%1 = call i64 asm sideeffect "fctid $0, $1", "=d,d"(double %0) #1, !srcloc !1
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store i64 %1, i64* %result, align 8
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%2 = load i64, i64* %result, align 8
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%conv = trunc i64 %2 to i32
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ret i32 %conv
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}
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attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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!0 = !{i32 67, i32 91, i32 110, i32 126}
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!1 = !{i32 84}
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