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f56c09c87f
If a resource can be held for multiple cycles in the schedule model then an instruction can be placed into the available queue, another instruction can be scheduled, but the first will not be taken back out if the two instructions hazard. To fix this make sure that we update the available queue even on the first MOp of a cycle, pushing available instructions back into the pending queue if they now conflict. This happens with some downstream schedules we have around MVE instruction scheduling where we use ResourceCycles=[2] to show the instruction executing over two beats. Apparently the test changes here are OK too. Differential Revision: https://reviews.llvm.org/D76909
27 lines
951 B
LLVM
27 lines
951 B
LLVM
; RUN: llc -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
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target datalayout = "E-m:e-p:32:32-i64:64-n32"
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target triple = "powerpc-buildroot-linux-gnu"
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@x = global ppc_fp128 0xM3FF00000000000000000000000000000, align 16
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@.str = private unnamed_addr constant [9 x i8] c"%Lf %Lf\0A\00", align 1
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define void @foo() #0 {
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entry:
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%0 = load ppc_fp128, ppc_fp128* @x, align 16
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%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), ppc_fp128 %0, ppc_fp128 %0)
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ret void
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}
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; Do not put second argument of function in r8 register, because there is no enough registers
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; left for long double type (4 registers in soft float mode). Instead in r8 register this
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; argument put on stack.
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; CHECK-NOT: mr 8, 4
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; CHECK: stw 6, 16(1)
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; CHECK: stw 7, 20(1)
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; CHECK: stw 5, 12(1)
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; CHECK: stw 4, 8(1)
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declare i32 @printf(i8* nocapture readonly, ...)
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attributes #0 = { "use-soft-float"="true" }
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