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8f83ef0f5e
Patch [4/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. We add SVE as unsupported feature for CPUs that don't have SVE to prevent errors from scheduler models saying it lacks information for these instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39090 llvm-svn: 317582
355 lines
15 KiB
TableGen
355 lines
15 KiB
TableGen
//==- AArch64SchedThunderX.td - Cavium ThunderX T8X Scheduling Definitions -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM ThunderX T8X
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// (T88, T81, T83) processors.
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// Loosely based on Cortex-A53 which is somewhat similar.
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//
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//===----------------------------------------------------------------------===//
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// ===---------------------------------------------------------------------===//
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// The following definitions describe the simpler per-operand machine model.
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// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
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// Cavium ThunderX T8X scheduling machine model.
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def ThunderXT8XModel : SchedMachineModel {
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let IssueWidth = 2; // 2 micro-ops dispatched per cycle.
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let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.
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let LoadLatency = 3; // Optimistic load latency.
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let MispredictPenalty = 8; // Branch mispredict penalty.
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let PostRAScheduler = 1; // Use PostRA scheduler.
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let CompleteModel = 1;
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list<Predicate> UnsupportedFeatures = [HasSVE];
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}
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// Modeling each pipeline with BufferSize == 0 since T8X is in-order.
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def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
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def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
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def THXT8XUnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
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def THXT8XUnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
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def THXT8XUnitBr : ProcResource<1> { let BufferSize = 0; } // Branch
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def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
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def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedWrite types mapping the ProcResources and
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// latencies.
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let SchedModel = ThunderXT8XModel in {
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// ALU
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def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; }
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def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
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def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
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def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
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def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
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def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
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// MAC
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def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
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let Latency = 4;
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let ResourceCycles = [1];
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}
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def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
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let Latency = 4;
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let ResourceCycles = [1];
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}
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// Div
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def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
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let Latency = 12;
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let ResourceCycles = [6];
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}
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def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
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let Latency = 14;
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let ResourceCycles = [8];
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}
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// Load
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def : WriteRes<WriteLD, [THXT8XUnitLdSt]> { let Latency = 3; }
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def : WriteRes<WriteLDIdx, [THXT8XUnitLdSt]> { let Latency = 3; }
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def : WriteRes<WriteLDHi, [THXT8XUnitLdSt]> { let Latency = 3; }
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// Vector Load
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def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
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let Latency = 8;
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let ResourceCycles = [3];
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}
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def THXT8XWriteVLD1 : SchedWriteRes<[THXT8XUnitLdSt]> {
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let Latency = 6;
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let ResourceCycles = [1];
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}
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def THXT8XWriteVLD2 : SchedWriteRes<[THXT8XUnitLdSt]> {
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let Latency = 11;
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let ResourceCycles = [7];
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}
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def THXT8XWriteVLD3 : SchedWriteRes<[THXT8XUnitLdSt]> {
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let Latency = 12;
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let ResourceCycles = [8];
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}
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def THXT8XWriteVLD4 : SchedWriteRes<[THXT8XUnitLdSt]> {
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let Latency = 13;
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let ResourceCycles = [9];
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}
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def THXT8XWriteVLD5 : SchedWriteRes<[THXT8XUnitLdSt]> {
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let Latency = 13;
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let ResourceCycles = [9];
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}
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// Pre/Post Indexing
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def : WriteRes<WriteAdr, []> { let Latency = 0; }
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// Store
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def : WriteRes<WriteST, [THXT8XUnitLdSt]> { let Latency = 1; }
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def : WriteRes<WriteSTP, [THXT8XUnitLdSt]> { let Latency = 1; }
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def : WriteRes<WriteSTIdx, [THXT8XUnitLdSt]> { let Latency = 1; }
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def : WriteRes<WriteSTX, [THXT8XUnitLdSt]> { let Latency = 1; }
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// Vector Store
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def : WriteRes<WriteVST, [THXT8XUnitLdSt]>;
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def THXT8XWriteVST1 : SchedWriteRes<[THXT8XUnitLdSt]>;
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def THXT8XWriteVST2 : SchedWriteRes<[THXT8XUnitLdSt]> {
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let Latency = 10;
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let ResourceCycles = [9];
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}
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def THXT8XWriteVST3 : SchedWriteRes<[THXT8XUnitLdSt]> {
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let Latency = 11;
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let ResourceCycles = [10];
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}
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def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
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// Branch
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def : WriteRes<WriteBr, [THXT8XUnitBr]>;
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def THXT8XWriteBR : SchedWriteRes<[THXT8XUnitBr]>;
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def : WriteRes<WriteBrReg, [THXT8XUnitBr]>;
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def THXT8XWriteBRR : SchedWriteRes<[THXT8XUnitBr]>;
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def THXT8XWriteRET : SchedWriteRes<[THXT8XUnitALU]>;
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def : WriteRes<WriteSys, [THXT8XUnitBr]>;
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def : WriteRes<WriteBarrier, [THXT8XUnitBr]>;
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def : WriteRes<WriteHint, [THXT8XUnitBr]>;
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// FP ALU
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def : WriteRes<WriteF, [THXT8XUnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteFCmp, [THXT8XUnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteFCvt, [THXT8XUnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteFCopy, [THXT8XUnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteFImm, [THXT8XUnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteV, [THXT8XUnitFPALU]> { let Latency = 6; }
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// FP Mul, Div, Sqrt
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def : WriteRes<WriteFMul, [THXT8XUnitFPMDS]> { let Latency = 6; }
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def : WriteRes<WriteFDiv, [THXT8XUnitFPMDS]> {
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let Latency = 22;
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let ResourceCycles = [19];
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}
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def THXT8XWriteFMAC : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 10; }
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def THXT8XWriteFDivSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
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let Latency = 12;
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let ResourceCycles = [9];
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}
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def THXT8XWriteFDivDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
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let Latency = 22;
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let ResourceCycles = [19];
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}
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def THXT8XWriteFSqrtSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
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let Latency = 17;
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let ResourceCycles = [14];
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}
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def THXT8XWriteFSqrtDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
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let Latency = 31;
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let ResourceCycles = [28];
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}
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedRead types.
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// No forwarding for these reads.
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def : ReadAdvance<ReadExtrHi, 1>;
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def : ReadAdvance<ReadAdrBase, 2>;
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def : ReadAdvance<ReadVLD, 2>;
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// FIXME: This needs more targeted benchmarking.
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// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
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// operands are needed one cycle later if and only if they are to be
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// shifted. Otherwise, they too are needed two cycles later. This same
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// ReadAdvance applies to Extended registers as well, even though there is
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// a separate SchedPredicate for them.
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def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
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WriteISReg, WriteIEReg, WriteIS,
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WriteID32, WriteID64,
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WriteIM32, WriteIM64]>;
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def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI,
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WriteISReg, WriteIEReg, WriteIS,
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WriteID32, WriteID64,
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WriteIM32, WriteIM64]>;
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def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
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WriteISReg, WriteIEReg, WriteIS,
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WriteID32, WriteID64,
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WriteIM32, WriteIM64]>;
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def THXT8XReadISReg : SchedReadVariant<[
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SchedVar<RegShiftedPred, [THXT8XReadShifted]>,
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SchedVar<NoSchedPred, [THXT8XReadNotShifted]>]>;
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def : SchedAlias<ReadISReg, THXT8XReadISReg>;
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def THXT8XReadIEReg : SchedReadVariant<[
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SchedVar<RegExtendedPred, [THXT8XReadShifted]>,
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SchedVar<NoSchedPred, [THXT8XReadNotShifted]>]>;
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def : SchedAlias<ReadIEReg, THXT8XReadIEReg>;
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// MAC - Operands are generally needed one cycle later in the MAC pipe.
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// Accumulator operands are needed two cycles later.
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def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
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WriteISReg, WriteIEReg, WriteIS,
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WriteID32, WriteID64,
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WriteIM32, WriteIM64]>;
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def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
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WriteISReg, WriteIEReg, WriteIS,
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WriteID32, WriteID64,
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WriteIM32, WriteIM64]>;
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// Div
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def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
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WriteISReg, WriteIEReg, WriteIS,
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WriteID32, WriteID64,
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WriteIM32, WriteIM64]>;
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//===----------------------------------------------------------------------===//
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// Subtarget-specific InstRW.
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//---
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// Branch
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//---
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def : InstRW<[THXT8XWriteBR], (instregex "^B$")>;
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def : InstRW<[THXT8XWriteBR], (instregex "^BL$")>;
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def : InstRW<[THXT8XWriteBR], (instregex "^B..$")>;
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def : InstRW<[THXT8XWriteBR], (instregex "^CBNZ")>;
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def : InstRW<[THXT8XWriteBR], (instregex "^CBZ")>;
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def : InstRW<[THXT8XWriteBR], (instregex "^TBNZ")>;
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def : InstRW<[THXT8XWriteBR], (instregex "^TBZ")>;
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def : InstRW<[THXT8XWriteBRR], (instregex "^BR$")>;
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def : InstRW<[THXT8XWriteBRR], (instregex "^BLR$")>;
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//---
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// Ret
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//---
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def : InstRW<[THXT8XWriteRET], (instregex "^RET$")>;
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//---
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// Miscellaneous
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//---
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def : InstRW<[WriteI], (instrs COPY)>;
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//---
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// Vector Loads
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//---
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def : InstRW<[THXT8XWriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
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def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
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def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
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def : InstRW<[THXT8XWriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
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def : InstRW<[THXT8XWriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
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def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[THXT8XWriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
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def : InstRW<[THXT8XWriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[THXT8XWriteVLD3], (instregex "LD3Threev(2d)$")>;
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def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
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def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
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def : InstRW<[THXT8XWriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
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def : InstRW<[THXT8XWriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[THXT8XWriteVLD4], (instregex "LD4Fourv(2d)$")>;
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def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
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def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
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//---
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// Vector Stores
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//---
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def : InstRW<[THXT8XWriteVST1], (instregex "ST1i(8|16|32|64)$")>;
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def : InstRW<[THXT8XWriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
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def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVST1], (instregex "ST2i(8|16|32|64)$")>;
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def : InstRW<[THXT8XWriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
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def : InstRW<[THXT8XWriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
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def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
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def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[THXT8XWriteVST2], (instregex "ST3i(8|16|32|64)$")>;
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def : InstRW<[THXT8XWriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[THXT8XWriteVST2], (instregex "ST3Threev(2d)$")>;
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def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
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def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
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def : InstRW<[THXT8XWriteVST2], (instregex "ST4i(8|16|32|64)$")>;
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def : InstRW<[THXT8XWriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[THXT8XWriteVST2], (instregex "ST4Fourv(2d)$")>;
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def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
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def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
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//---
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// Floating Point MAC, DIV, SQRT
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//---
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def : InstRW<[THXT8XWriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
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def : InstRW<[THXT8XWriteFMAC], (instregex "^FML(A|S).*")>;
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def : InstRW<[THXT8XWriteFDivSP], (instrs FDIVSrr)>;
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def : InstRW<[THXT8XWriteFDivDP], (instrs FDIVDrr)>;
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def : InstRW<[THXT8XWriteFDivSP], (instregex "^FDIVv.*32$")>;
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def : InstRW<[THXT8XWriteFDivDP], (instregex "^FDIVv.*64$")>;
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def : InstRW<[THXT8XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
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def : InstRW<[THXT8XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
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}
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