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e84c6abeec
This patch adds patterns to generate the cls instruction ARM64. Includes tests for 64 bit and 32 bit operands. rdar://15611957 llvm-svn: 206079
37 lines
878 B
LLVM
37 lines
878 B
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios7.0.0"
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; Function Attrs: nounwind readnone
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declare i32 @llvm.ctlz.i32(i32, i1) #0
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declare i64 @llvm.ctlz.i64(i64, i1) #1
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; Function Attrs: nounwind ssp
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define i32 @clrsb32(i32 %x) #2 {
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entry:
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%shr = ashr i32 %x, 31
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%xor = xor i32 %shr, %x
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%mul = shl i32 %xor, 1
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%add = or i32 %mul, 1
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%0 = tail call i32 @llvm.ctlz.i32(i32 %add, i1 false)
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ret i32 %0
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; CHECK-LABEL: clrsb32
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; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]]
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}
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; Function Attrs: nounwind ssp
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define i64 @clrsb64(i64 %x) #3 {
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entry:
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%shr = ashr i64 %x, 63
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%xor = xor i64 %shr, %x
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%mul = shl nsw i64 %xor, 1
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%add = or i64 %mul, 1
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%0 = tail call i64 @llvm.ctlz.i64(i64 %add, i1 false)
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ret i64 %0
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; CHECK-LABEL: clrsb64
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; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]]
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}
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