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https://github.com/RPCS3/llvm-mirror.git
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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
74 lines
2.2 KiB
LLVM
74 lines
2.2 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <2 x float> @ucvt(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: ucvt:
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; CHECK: ucvtf.2s v0, v0
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; CHECK: ret
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%vcvt.i = uitofp <2 x i32> %a to <2 x float>
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ret <2 x float> %vcvt.i
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}
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define <2 x float> @scvt(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: scvt:
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; CHECK: scvtf.2s v0, v0
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; CHECK: ret
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%vcvt.i = sitofp <2 x i32> %a to <2 x float>
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ret <2 x float> %vcvt.i
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}
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define <4 x float> @ucvtq(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: ucvtq:
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; CHECK: ucvtf.4s v0, v0
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; CHECK: ret
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%vcvt.i = uitofp <4 x i32> %a to <4 x float>
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ret <4 x float> %vcvt.i
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}
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define <4 x float> @scvtq(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: scvtq:
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; CHECK: scvtf.4s v0, v0
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; CHECK: ret
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%vcvt.i = sitofp <4 x i32> %a to <4 x float>
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ret <4 x float> %vcvt.i
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}
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define <4 x float> @cvtf16(<4 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtf16:
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; CHECK: fcvtl v0.4s, v0.4h
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; CHECK-NEXT: ret
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%vcvt1.i = tail call <4 x float> @llvm.arm64.neon.vcvthf2fp(<4 x i16> %a) nounwind
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ret <4 x float> %vcvt1.i
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}
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define <4 x float> @cvtf16_high(<8 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtf16_high:
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; CHECK: fcvtl2 v0.4s, v0.8h
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; CHECK-NEXT: ret
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%in = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%vcvt1.i = tail call <4 x float> @llvm.arm64.neon.vcvthf2fp(<4 x i16> %in) nounwind
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ret <4 x float> %vcvt1.i
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}
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define <4 x i16> @cvtf16f32(<4 x float> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtf16f32:
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; CHECK: fcvtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%vcvt1.i = tail call <4 x i16> @llvm.arm64.neon.vcvtfp2hf(<4 x float> %a) nounwind
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ret <4 x i16> %vcvt1.i
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}
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define <8 x i16> @cvtf16f32_high(<4 x i16> %low, <4 x float> %high_big) {
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; CHECK-LABEL: cvtf16f32_high:
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; CHECK: fcvtn2 v0.8h, v1.4s
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; CHECK-NEXT: ret
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%high = call <4 x i16> @llvm.arm64.neon.vcvtfp2hf(<4 x float> %high_big)
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%res = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %res
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}
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declare <4 x float> @llvm.arm64.neon.vcvthf2fp(<4 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm64.neon.vcvtfp2hf(<4 x float>) nounwind readnone
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