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111 lines
4.6 KiB
C++
111 lines
4.6 KiB
C++
//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 Register file, defining the registers themselves,
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// aliases between the registers, and the register classes built out of the
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// registers.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register definitions...
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//
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let Namespace = "X86" in {
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// In the register alias definitions below, we define which registers alias
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// which others. We only specify which registers the small registers alias,
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// because the register file generator is smart enough to figure out that
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// AL aliases AX if we tell it that AX aliased AL (for example).
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// 32-bit registers
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def EAX : Register<"EAX">; def ECX : Register<"ECX">;
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def EDX : Register<"EDX">; def EBX : Register<"EBX">;
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def ESP : Register<"ESP">; def EBP : Register<"EBP">;
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def ESI : Register<"ESI">; def EDI : Register<"EDI">;
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// 16-bit registers
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def AX : RegisterGroup<"AX", [EAX]>; def CX : RegisterGroup<"CX", [ECX]>;
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def DX : RegisterGroup<"DX", [EDX]>; def BX : RegisterGroup<"BX", [EBX]>;
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def SP : RegisterGroup<"SP", [ESP]>; def BP : RegisterGroup<"BP", [EBP]>;
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def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
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// 8-bit registers
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def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>;
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def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>;
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def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>;
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def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>;
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// Pseudo Floating Point registers
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def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;
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def FP2 : Register<"FP2">; def FP3 : Register<"FP3">;
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def FP4 : Register<"FP4">; def FP5 : Register<"FP5">;
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def FP6 : Register<"FP6">;
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// Floating point stack registers
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def ST0 : Register<"ST(0)">; def ST1 : Register<"ST(1)">;
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def ST2 : Register<"ST(2)">; def ST3 : Register<"ST(3)">;
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def ST4 : Register<"ST(4)">; def ST5 : Register<"ST(5)">;
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def ST6 : Register<"ST(6)">; def ST7 : Register<"ST(7)">;
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// Flags, Segment registers, etc...
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}
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//===----------------------------------------------------------------------===//
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// Register Class Definitions... now that we have all of the pieces, define the
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// top-level register classes. The order specified in the register list is
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// implicitly defined to be the register allocation order.
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//
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// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
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// dependences between upper and lower parts of the register. BL and BH are
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// last because they are call clobbered. Both Athlon and P4 chips suffer this
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// issue.
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def R8 : RegisterClass<i8, 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
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def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate SP or BP
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else
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return end()-1; // If not, just don't allocate SP
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}
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}];
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}
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def R32 : RegisterClass<i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate ESP or EBP
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else
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return end()-1; // If not, just don't allocate ESP
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}
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}];
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}
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// FIXME: This sets up the floating point register files as though they are f64
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// values, though they really are f80 values. This will cause us to spill
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// values as 64-bit quantities instead of 80-bit quantities, which is much much
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// faster on common hardware. In reality, this should be controlled by a
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// command line option or something.
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def RFP : RegisterClass<f64, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
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// Floating point stack registers (these are not allocatable by the
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// register allocator - the floating point stackifier is responsible
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// for transforming FPn allocations to STn registers)
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def RST : RegisterClass<f64, 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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return begin();
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}
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}];
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}
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