1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
llvm-mirror/test/CodeGen/ARM/fpmem.ll
Jim Grosbach 4a2f107b04 ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
2011-11-14 23:03:21 +00:00

42 lines
1.0 KiB
LLVM

; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define float @f1(float %a) {
; CHECK: f1:
; CHECK: mov r0, #0
ret float 0.000000e+00
}
define float @f2(float* %v, float %u) {
; CHECK: f2:
; CHECK: vldr{{.*}}[
%tmp = load float* %v ; <float> [#uses=1]
%tmp1 = fadd float %tmp, %u ; <float> [#uses=1]
ret float %tmp1
}
define float @f2offset(float* %v, float %u) {
; CHECK: f2offset:
; CHECK: vldr{{.*}}, #4]
%addr = getelementptr float* %v, i32 1
%tmp = load float* %addr
%tmp1 = fadd float %tmp, %u
ret float %tmp1
}
define float @f2noffset(float* %v, float %u) {
; CHECK: f2noffset:
; CHECK: vldr{{.*}}, #-4]
%addr = getelementptr float* %v, i32 -1
%tmp = load float* %addr
%tmp1 = fadd float %tmp, %u
ret float %tmp1
}
define void @f3(float %a, float %b, float* %v) {
; CHECK: f3:
; CHECK: vstr{{.*}}[
%tmp = fadd float %a, %b ; <float> [#uses=1]
store float %tmp, float* %v
ret void
}