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793fa215cb
We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. llvm-svn: 148568
401 lines
11 KiB
LLVM
401 lines
11 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @v_movi8() nounwind {
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;CHECK: v_movi8:
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;CHECK: vmov.i8 d{{.*}}, #0x8
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ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <4 x i16> @v_movi16a() nounwind {
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;CHECK: v_movi16a:
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;CHECK: vmov.i16 d{{.*}}, #0x10
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ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
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}
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define <4 x i16> @v_movi16b() nounwind {
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;CHECK: v_movi16b:
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;CHECK: vmov.i16 d{{.*}}, #0x1000
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ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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define <4 x i16> @v_mvni16a() nounwind {
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;CHECK: v_mvni16a:
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;CHECK: vmvn.i16 d{{.*}}, #0x10
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ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
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}
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define <4 x i16> @v_mvni16b() nounwind {
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;CHECK: v_mvni16b:
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;CHECK: vmvn.i16 d{{.*}}, #0x1000
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ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
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}
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define <2 x i32> @v_movi32a() nounwind {
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;CHECK: v_movi32a:
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;CHECK: vmov.i32 d{{.*}}, #0x20
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ret <2 x i32> < i32 32, i32 32 >
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}
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define <2 x i32> @v_movi32b() nounwind {
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;CHECK: v_movi32b:
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;CHECK: vmov.i32 d{{.*}}, #0x2000
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ret <2 x i32> < i32 8192, i32 8192 >
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}
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define <2 x i32> @v_movi32c() nounwind {
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;CHECK: v_movi32c:
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;CHECK: vmov.i32 d{{.*}}, #0x200000
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ret <2 x i32> < i32 2097152, i32 2097152 >
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}
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define <2 x i32> @v_movi32d() nounwind {
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;CHECK: v_movi32d:
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;CHECK: vmov.i32 d{{.*}}, #0x20000000
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ret <2 x i32> < i32 536870912, i32 536870912 >
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}
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define <2 x i32> @v_movi32e() nounwind {
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;CHECK: v_movi32e:
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;CHECK: vmov.i32 d{{.*}}, #0x20ff
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ret <2 x i32> < i32 8447, i32 8447 >
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}
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define <2 x i32> @v_movi32f() nounwind {
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;CHECK: v_movi32f:
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;CHECK: vmov.i32 d{{.*}}, #0x20ffff
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ret <2 x i32> < i32 2162687, i32 2162687 >
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}
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define <2 x i32> @v_mvni32a() nounwind {
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;CHECK: v_mvni32a:
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;CHECK: vmvn.i32 d{{.*}}, #0x20
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ret <2 x i32> < i32 4294967263, i32 4294967263 >
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}
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define <2 x i32> @v_mvni32b() nounwind {
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;CHECK: v_mvni32b:
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;CHECK: vmvn.i32 d{{.*}}, #0x2000
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ret <2 x i32> < i32 4294959103, i32 4294959103 >
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}
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define <2 x i32> @v_mvni32c() nounwind {
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;CHECK: v_mvni32c:
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;CHECK: vmvn.i32 d{{.*}}, #0x200000
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ret <2 x i32> < i32 4292870143, i32 4292870143 >
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}
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define <2 x i32> @v_mvni32d() nounwind {
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;CHECK: v_mvni32d:
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;CHECK: vmvn.i32 d{{.*}}, #0x20000000
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ret <2 x i32> < i32 3758096383, i32 3758096383 >
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}
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define <2 x i32> @v_mvni32e() nounwind {
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;CHECK: v_mvni32e:
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;CHECK: vmvn.i32 d{{.*}}, #0x20ff
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ret <2 x i32> < i32 4294958848, i32 4294958848 >
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}
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define <2 x i32> @v_mvni32f() nounwind {
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;CHECK: v_mvni32f:
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;CHECK: vmvn.i32 d{{.*}}, #0x20ffff
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ret <2 x i32> < i32 4292804608, i32 4292804608 >
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}
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define <1 x i64> @v_movi64() nounwind {
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;CHECK: v_movi64:
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;CHECK: vmov.i64 d{{.*}}, #0xff0000ff0000ffff
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ret <1 x i64> < i64 18374687574888349695 >
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}
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define <16 x i8> @v_movQi8() nounwind {
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;CHECK: v_movQi8:
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;CHECK: vmov.i8 q{{.*}}, #0x8
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ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <8 x i16> @v_movQi16a() nounwind {
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;CHECK: v_movQi16a:
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;CHECK: vmov.i16 q{{.*}}, #0x10
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ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
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}
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define <8 x i16> @v_movQi16b() nounwind {
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;CHECK: v_movQi16b:
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;CHECK: vmov.i16 q{{.*}}, #0x1000
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ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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define <4 x i32> @v_movQi32a() nounwind {
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;CHECK: v_movQi32a:
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;CHECK: vmov.i32 q{{.*}}, #0x20
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ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
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}
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define <4 x i32> @v_movQi32b() nounwind {
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;CHECK: v_movQi32b:
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;CHECK: vmov.i32 q{{.*}}, #0x2000
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ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
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}
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define <4 x i32> @v_movQi32c() nounwind {
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;CHECK: v_movQi32c:
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;CHECK: vmov.i32 q{{.*}}, #0x200000
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ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
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}
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define <4 x i32> @v_movQi32d() nounwind {
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;CHECK: v_movQi32d:
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;CHECK: vmov.i32 q{{.*}}, #0x20000000
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ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
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}
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define <4 x i32> @v_movQi32e() nounwind {
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;CHECK: v_movQi32e:
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;CHECK: vmov.i32 q{{.*}}, #0x20ff
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ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
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}
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define <4 x i32> @v_movQi32f() nounwind {
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;CHECK: v_movQi32f:
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;CHECK: vmov.i32 q{{.*}}, #0x20ffff
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ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
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}
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define <2 x i64> @v_movQi64() nounwind {
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;CHECK: v_movQi64:
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;CHECK: vmov.i64 q{{.*}}, #0xff0000ff0000ffff
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ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
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}
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; Check for correct assembler printing for immediate values.
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%struct.int8x8_t = type { <8 x i8> }
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define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
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entry:
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;CHECK: vdupn128:
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;CHECK: vmov.i8 d{{.*}}, #0x80
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%0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
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store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
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ret void
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}
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define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
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entry:
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;CHECK: vdupnneg75:
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;CHECK: vmov.i8 d{{.*}}, #0xb5
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%0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
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store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
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ret void
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}
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define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
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;CHECK: vmovls8:
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;CHECK: vmovl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
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;CHECK: vmovls16:
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;CHECK: vmovl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
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;CHECK: vmovls32:
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;CHECK: vmovl.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
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ret <2 x i64> %tmp2
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}
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define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
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;CHECK: vmovlu8:
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;CHECK: vmovl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
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;CHECK: vmovlu16:
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;CHECK: vmovl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
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;CHECK: vmovlu32:
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;CHECK: vmovl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
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ret <2 x i64> %tmp2
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}
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define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
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;CHECK: vmovni16:
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;CHECK: vmovn.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
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;CHECK: vmovni32:
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;CHECK: vmovn.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
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;CHECK: vmovni64:
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;CHECK: vmovn.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovns16:
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;CHECK: vqmovn.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovns32:
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;CHECK: vqmovn.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovns64:
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;CHECK: vqmovn.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovnu16:
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;CHECK: vqmovn.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovnu32:
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;CHECK: vqmovn.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovnu64:
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;CHECK: vqmovn.u64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovuns16:
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;CHECK: vqmovun.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovuns32:
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;CHECK: vqmovun.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovuns64:
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;CHECK: vqmovun.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
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; Truncating vector stores are not supported. The following should not crash.
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; Radar 8598391.
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define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind {
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;CHECK: vmovn
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%tmp1 = load <4 x i32>* %a, align 16
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%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
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store <4 x i16> %tmp2, <4 x i16>* %b, align 8
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ret void
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}
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; Use vmov.f32 to materialize f32 immediate splats
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; rdar://10437054
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define void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind {
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entry:
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;CHECK: v_mov_v2f32:
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;CHECK: vmov.f32 d{{.*}}, #-1.600000e+01
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store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4
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ret void
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}
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define void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind {
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entry:
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;CHECK: v_mov_v4f32:
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;CHECK: vmov.f32 q{{.*}}, #3.100000e+01
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store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4
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ret void
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}
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define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind {
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entry:
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;CHECK: v_mov_v4f32_undef:
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;CHECK: vmov.f32 q{{.*}}, #1.000000e+00
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%a = load <4 x float> *%p
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%b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>
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store <4 x float> %b, <4 x float> *%p
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ret void
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}
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; Vector any_extends must be selected as either vmovl.u or vmovl.s.
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; rdar://10723651
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define void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp {
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entry:
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;CHECK: any_extend
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;CHECK: vmovl
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%and.i186 = zext <4 x i1> %x to <4 x i32>
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%add.i185 = sub <4 x i32> %and.i186, %y
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%sub.i = sub <4 x i32> %add.i185, zeroinitializer
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%add.i = add <4 x i32> %sub.i, zeroinitializer
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%vmovn.i = trunc <4 x i32> %add.i to <4 x i16>
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tail call void @llvm.arm.neon.vst1.v4i16(i8* undef, <4 x i16> %vmovn.i, i32 2)
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unreachable
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}
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declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind
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