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llvm-mirror/test/CodeGen
Alex Lorenz c21c095194 MIR Serialization: Change MIR syntax - use custom syntax for MBBs.
This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.

This is an example of a function's body that uses the old syntax:

    body:
      - id: 0
        name: entry
        instructions:
          - '%eax = MOV32r0 implicit-def %eflags'
          - 'RETQ %eax'
    ...

The same body is now written like this:

    body: |
      bb.0.entry:
        %eax = MOV32r0 implicit-def %eflags
        RETQ %eax
    ...

This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:

   BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
      t2IT 1, 24, implicit-def %itstate
      %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
   }

This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.

llvm-svn: 244982
2015-08-13 23:10:16 +00:00
..
AArch64 [AArch64] Small rejig of fmax tests, NFCI. 2015-08-13 17:28:10 +00:00
AMDGPU AMDGPU: Fix assert on dbg_value instructions 2015-08-12 09:04:44 +00:00
ARM [ARM] Rejig vmax tests a bit 2015-08-13 17:28:16 +00:00
BPF [bpf] rename triple names bpf_be -> bpfeb 2015-06-05 16:11:14 +00:00
CPP
Generic Update test suite to make "ninja check" succeed without native backend builtin 2015-08-04 06:32:54 +00:00
Hexagon DI: Disallow uniquable DICompileUnits 2015-08-03 17:26:41 +00:00
Inputs DI: Disallow uniquable DICompileUnits 2015-08-03 17:26:41 +00:00
Mips Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions. 2015-08-04 14:26:35 +00:00
MIR MIR Serialization: Change MIR syntax - use custom syntax for MBBs. 2015-08-13 23:10:16 +00:00
MSP430
NVPTX Use 32-bit divides instead of 64-bit divides where possible. 2015-08-11 22:16:34 +00:00
PowerPC Scalar to vector conversions using direct moves 2015-08-13 17:40:44 +00:00
SPARC [Sparc] Implement i64 load/store support for 32-bit sparc. 2015-08-10 19:11:39 +00:00
SystemZ [SystemZ] Support large LLVM IR struct return values 2015-08-13 13:37:06 +00:00
Thumb DI: Disallow uniquable DICompileUnits 2015-08-03 17:26:41 +00:00
Thumb2 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 2015-07-21 00:18:59 +00:00
WebAssembly WebAssembly: floating-point comparisons 2015-08-12 17:53:29 +00:00
WinEH [WinEHPrepare] Update demotion logic 2015-08-13 14:30:10 +00:00
X86 MIR Serialization: Change MIR syntax - use custom syntax for MBBs. 2015-08-13 23:10:16 +00:00
XCore DI: Disallow uniquable DICompileUnits 2015-08-03 17:26:41 +00:00